gustavonihei opened a new issue #3483: URL: https://github.com/apache/incubator-nuttx/issues/3483
GCC does not provide the low-level implementation of the C11 Atomic operations for CPUs that don't provide the appropriate ISA support [1][2]. So the C11 atomic operations have been implemented [3] for ESP32-C3 with support from NuttX, since the ESP32-C3 RISC-V ISA does not implement the atomics (A) extension. The same implementation could be reused by other CPUs the don't provide atomic load/store instructions, e.g. Cortex-M0+, which being based on the armv6-m does not provide the Load-Exclusive and Store-Exclusive instructions from armv7-m. This is also required for using some C++ standard library functions, e.g. `std::mutex`. [1] https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary [2] https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html [3] https://github.com/apache/incubator-nuttx/blob/master/arch/risc-v/src/esp32c3/esp32c3_std_atomic.c -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: [email protected]
