xiaoxiang781216 commented on a change in pull request #3626:
URL: https://github.com/apache/incubator-nuttx/pull/3626#discussion_r640787605
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File path: arch/risc-v/src/rv64gc/riscv_swint.c
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@@ -282,33 +282,64 @@ int riscv_swint(int irq, FAR void *context, FAR void *arg)
break;
#endif
- /* R0=SYS_pthread_start: This a user pthread start
+#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD)
+
+ /* A0=SYS_pthread_start: This a user pthread start
*
- * void up_pthread_start(pthread_startroutine_t entrypt,
- * pthread_addr_t arg) noreturn_function;
+ * void up_pthread_start(pthread_trampoline_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
*
* At this point, the following values are saved in context:
*
- * R0 = SYS_pthread_start
- * R1 = entrypt
- * R2 = arg
+ * A0 = SYS_pthread_start
+ * A1 = startup
+ * A2 = entrypt
+ * A3 = arg
*/
-#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_PTHREAD)
case SYS_pthread_start:
{
/* Set up to return to the user-space pthread start-up function in
* unprivileged mode.
*/
- regs[REG_EPC] = (uintptr_t)USERSPACE->pthread_startup & ~1;
+ regs[REG_EPC] = (uintptr_t)regs[REG_A1] & ~1; /* startup */
Review comment:
RISC-V use the mix encoding(instruction length can be 2bytes or 4bytes),
so it don't have something like ARM/THUMB, and the bit0 is always zero. The
mask can be removed safely.
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