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commit b57e0b6118feab02d88cce39cacb745950f02a0d
Author: chao.an <anc...@xiaomi.com>
AuthorDate: Sun Feb 27 12:55:08 2022 +0800
arm/armv7-a/r: check ARMV7A_DECODEFIQ on dataabort
Signed-off-by: chao.an <anc...@xiaomi.com>
---
arch/arm/src/armv7-a/arm_vectors.S | 12 ++++++++++++
arch/arm/src/armv7-r/arm_vectors.S | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/src/armv7-a/arm_vectors.S
b/arch/arm/src/armv7-a/arm_vectors.S
index f3a2319..0036fba 100644
--- a/arch/arm/src/armv7-a/arm_vectors.S
+++ b/arch/arm/src/armv7-a/arm_vectors.S
@@ -423,7 +423,11 @@ arm_vectordata:
* r13 and r14
*/
+#ifdef CONFIG_ARMV7A_DECODEFIQ
mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
msr cpsr_c, r13 /* Switch to SVC mode */
/* Create a context structure. First set aside a stack frame
@@ -433,7 +437,11 @@ arm_vectordata:
sub sp, sp, #XCPTCONTEXT_SIZE
stmia sp, {r0-r12} /* Save the SVC mode
regs */
+#ifdef CONFIG_ARMV7A_DECODEFIQ
mov r0, #(PSR_MODE_ABT | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_ABT | PSR_I_BIT)
+#endif
msr cpsr_c, r0 /* Switch back ABT mode
*/
/* Get the values for r15(pc) and CPSR in r3 and r4 */
@@ -443,7 +451,11 @@ arm_vectordata:
/* Then switch back to SVC mode */
+#ifdef CONFIG_ARMV7A_DECODEFIQ
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
msr cpsr_c, r0
#ifdef CONFIG_BUILD_KERNEL
diff --git a/arch/arm/src/armv7-r/arm_vectors.S
b/arch/arm/src/armv7-r/arm_vectors.S
index 64d1190..8c5f88c 100644
--- a/arch/arm/src/armv7-r/arm_vectors.S
+++ b/arch/arm/src/armv7-r/arm_vectors.S
@@ -377,7 +377,11 @@ arm_vectordata:
* r13 and r14
*/
+#ifdef CONFIG_ARMV7A_DECODEFIQ
mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
msr cpsr_c, r13 /* Switch to SVC mode */
/* Create a context structure. First set aside a stack frame
@@ -387,7 +391,11 @@ arm_vectordata:
sub sp, sp, #XCPTCONTEXT_SIZE
stmia sp, {r0-r12} /* Save the SVC mode
regs */
+#ifdef CONFIG_ARMV7A_DECODEFIQ
mov r0, #(PSR_MODE_ABT | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_ABT | PSR_I_BIT)
+#endif
msr cpsr_c, r0 /* Switch back ABT mode
*/
/* Get the values for r15(pc) and CPSR in r3 and r4 */
@@ -397,7 +405,11 @@ arm_vectordata:
/* Then switch back to SVC mode */
+#ifdef CONFIG_ARMV7A_DECODEFIQ
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
msr cpsr_c, r0
#ifdef CONFIG_BUILD_PROTECTED
