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new 72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602
72e79aa0f1 is described below
commit 72e79aa0f10416bdede64c6ffc09adabdefebe2b
Author: Huang Qi <[email protected]>
AuthorDate: Mon Apr 11 09:47:53 2022 +0800
arch/risc-v: Apply misaligned access handler for k210/bl602
Signed-off-by: Huang Qi <[email protected]>
---
arch/risc-v/Kconfig | 13 +++++++++++++
arch/risc-v/src/bl602/Make.defs | 2 +-
arch/risc-v/src/common/riscv_exception.c | 10 ++++++++--
arch/risc-v/src/k210/Make.defs | 1 +
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
index 8664f13c01..fc8ff42229 100644
--- a/arch/risc-v/Kconfig
+++ b/arch/risc-v/Kconfig
@@ -30,6 +30,7 @@ config ARCH_CHIP_K210
select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_MULTICPU
+ select ARCH_HAVE_MISALIGN_EXCEPTION
select ONESHOT
select ALARM_ARCH
---help---
@@ -52,6 +53,7 @@ config ARCH_CHIP_BL602
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_RESET
+ select ARCH_HAVE_MISALIGN_EXCEPTION
select ONESHOT
select ALARM_ARCH
---help---
@@ -206,6 +208,17 @@ config ARCH_HAVE_S_MODE
bool
default n
+config ARCH_HAVE_MISALIGN_EXCEPTION
+ bool
+ default n
+ ---help---
+ The chip will raise a exception while misaligned memory access.
+
+config RISCV_MISALIGNED_HANDLER
+ bool "Software misaligned memory access handler"
+ depends on ARCH_HAVE_MISALIGN_EXCEPTION
+ default y
+
# Option to run NuttX in supervisor mode. This is obviously not usable in
# flat mode, is questionable in protected mode, but is mandatory in kernel
# mode.
diff --git a/arch/risc-v/src/bl602/Make.defs b/arch/risc-v/src/bl602/Make.defs
index 4f9df8ddbf..37203055fd 100644
--- a/arch/risc-v/src/bl602/Make.defs
+++ b/arch/risc-v/src/bl602/Make.defs
@@ -34,7 +34,7 @@ CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c
riscv_usestack.c
CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_getnewintctx.c riscv_doirq.c
-CMN_CSRCS += riscv_exception.c riscv_mtimer.c
+CMN_CSRCS += riscv_exception.c riscv_mtimer.c riscv_misaligned.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += riscv_backtrace.c
diff --git a/arch/risc-v/src/common/riscv_exception.c
b/arch/risc-v/src/common/riscv_exception.c
index 3e5bc60259..256625ddee 100644
--- a/arch/risc-v/src/common/riscv_exception.c
+++ b/arch/risc-v/src/common/riscv_exception.c
@@ -105,11 +105,17 @@ void riscv_exception_attach(void)
irq_attach(RISCV_IRQ_IAFAULT, riscv_exception, NULL);
irq_attach(RISCV_IRQ_IINSTRUCTION, riscv_exception, NULL);
irq_attach(RISCV_IRQ_BPOINT, riscv_exception, NULL);
- irq_attach(RISCV_IRQ_LAMISALIGNED, riscv_exception, NULL);
irq_attach(RISCV_IRQ_LAFAULT, riscv_exception, NULL);
- irq_attach(RISCV_IRQ_SAMISALIGNED, riscv_exception, NULL);
irq_attach(RISCV_IRQ_SAFAULT, riscv_exception, NULL);
+#ifdef CONFIG_RISCV_MISALIGNED_HANDLER
+ irq_attach(RISCV_IRQ_LAMISALIGNED, riscv_misaligned, NULL);
+ irq_attach(RISCV_IRQ_SAMISALIGNED, riscv_misaligned, NULL);
+#else
+ irq_attach(RISCV_IRQ_LAMISALIGNED, riscv_exception, NULL);
+ irq_attach(RISCV_IRQ_SAMISALIGNED, riscv_exception, NULL);
+#endif
+
/* Attach the ecall interrupt handler */
#ifndef CONFIG_BUILD_FLAT
diff --git a/arch/risc-v/src/k210/Make.defs b/arch/risc-v/src/k210/Make.defs
index 5b49d5914e..89bec1c201 100644
--- a/arch/risc-v/src/k210/Make.defs
+++ b/arch/risc-v/src/k210/Make.defs
@@ -35,6 +35,7 @@ CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c
riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
CMN_CSRCS += riscv_mdelay.c riscv_idle.c riscv_doirq.c
CMN_CSRCS += riscv_tcbinfo.c riscv_cpuidlestack.c riscv_getnewintctx.c
+CMN_CSRCS += riscv_misaligned.c
ifeq ($(CONFIG_SMP), y)
CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c
