jnippula opened a new pull request, #8700: URL: https://github.com/apache/nuttx/pull/8700
## Summary In mpfs spi_irq handler the data is written into txfifo and transfer is started before the TXDONE interrupt is cleared. If the bus/memory access is in some cases delayed, the SPI transfer may have been finished already before the interrupt register is cleaned for the transfer. ## Impact Previous implementation leads the early arrived interrupt to be just removed and never handled, which would cause a timeout error. This fix moves the clearing of the interrupt to the place before the TX is started, so the interrupt is not missed in above cases. ## Testing Fix is tested in dual OS system (Nuttx & Linux), where high CPU load in other OS slows down the bus/memory accesses in Nuttx side. This test setup triggers the SPI TX Timeout errors while reading peripheral registers via SPI bus. With this fix there are no SPI TX timeout errors seen in the same test setup. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
