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The following commit(s) were added to refs/heads/master by this push:
new aeddec2ec5 clear i2c ints before the transfer starts
aeddec2ec5 is described below
commit aeddec2ec549ccfdb25879a0f81c72a729748ce9
Author: Jari Nippula <[email protected]>
AuthorDate: Wed Mar 1 09:55:22 2023 +0200
clear i2c ints before the transfer starts
If transfer is restarted in irq handler the interrupts shall be
cleared before the start bit is set in control register. This is
to avoid ints being accidentally cleared before they are handled leading
to timeout error.
---
arch/risc-v/src/mpfs/mpfs_i2c.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/risc-v/src/mpfs/mpfs_i2c.c b/arch/risc-v/src/mpfs/mpfs_i2c.c
index 5e7bde97b0..8ca4f1b20a 100644
--- a/arch/risc-v/src/mpfs/mpfs_i2c.c
+++ b/arch/risc-v/src/mpfs/mpfs_i2c.c
@@ -396,6 +396,11 @@ static int mpfs_i2c_irq(int cpuint, void *context, void
*arg)
break;
case MPFS_I2C_ST_LOST_ARB:
+
+ /* Clear interrupt. */
+
+ modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0);
+ clear_irq = 0u;
modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STA_MASK,
MPFS_I2C_CTRL_STA_MASK);
break;
@@ -416,6 +421,10 @@ static int mpfs_i2c_irq(int cpuint, void *context, void
*arg)
}
else if (msg->flags & I2C_M_NOSTOP)
{
+ /* Clear interrupt. */
+
+ modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0);
+ clear_irq = 0u;
modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_STA_MASK,
MPFS_I2C_CTRL_STA_MASK);