xiaoxiang781216 commented on code in PR #9853:
URL: https://github.com/apache/nuttx/pull/9853#discussion_r1271402367
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -284,7 +275,63 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
+ default y
+
+config STM32U5_SRAM2
+ bool "SRAM2"
+ default n
+
+config STM32U5_SRAM3
+ bool "SRAM3"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+config STM32U5_SRAM5
+ bool "SRAM5"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+comment "SRAM Options"
+
+config STM32U5_SRAM2_HEAP
+ bool "SRAM2 is used for heap"
default n
+ depends on STM32U5_SRAM2
Review Comment:
```suggestion
depends on STM32U5_SRAM2
```
##########
arch/arm/include/stm32u5/stm32u5xx_irq.h:
##########
@@ -128,7 +128,15 @@
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global
interrupt */
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global
interrupt */
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2
interrupts */
-#define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS
global interrupt */
+#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX)
|| \
+ defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX)
+# define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS
global interrupt */
+#elif defined(CONFIG_STM32U5_STM32U59XX) ||
defined(CONFIG_STM32U5_STM32U59AXX) || \
+ defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
+# define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS
global interrupt */
Review Comment:
```suggestion
# define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS
global interrupt */
```
##########
arch/arm/src/stm32u5/hardware/stm32_flash.h:
##########
@@ -70,11 +71,18 @@
#else
# error "unknown flash configuration!"
#endif
+#endif
#ifdef STM32_FLASH_PAGESIZE
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
#endif
+#if defined(CONFIG_STM32U5_STM32U5A5XX)
+# define STM32_FLASH_NPAGES 512
Review Comment:
```suggestion
# define STM32_FLASH_NPAGES 512
```
change all tab to space in *.h/*.c, tab is only in Kconfig and *.S.
##########
arch/arm/src/stm32u5/hardware/stm32_flash.h:
##########
@@ -41,6 +41,7 @@
* Parts STM32U585 and STM32U575 have 2048Kb of FLASH
*/
+#if defined(CONFIG_ARCH_CHIP_STM32U585AI)
#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \
Review Comment:
Unchange, you need either merge two #if into one, or indent the second #if
##########
boards/Kconfig:
##########
@@ -3114,7 +3114,7 @@ config ARCH_BOARD
default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1
default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A
default "b-u585i-iot02a" if ARCH_BOARD_B_U585I_IOT02A
- default "nucleo-u5a5zj-q" if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
+ default "nucleo-u5a5zj-q"
if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
Review Comment:
```suggestion
default "nucleo-u5a5zj-q" if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
```
AGAIN, DON'T USE TAB IN SOURCE CODE.
##########
arch/arm/src/stm32u5/stm32_allocateheap.c:
##########
@@ -350,6 +357,26 @@ void arm_addregion(void)
#endif /* SRAM3 */
+#ifdef CONFIG_STM32U5_SRAM5_HEAP
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
Review Comment:
unchange
##########
arch/arm/src/stm32u5/hardware/stm32_memorymap.h:
##########
@@ -43,11 +43,34 @@
/* Code Base Addresses ******************************************************/
-#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased
boot memory */
-#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH
memory */
-#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k
SRAM1 */
-#define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k
SRAM2 */
-#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k
SRAM3 */
+#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX)
+# define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff:
Aliased boot memory */
Review Comment:
```suggestion
# define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff:
Aliased boot memory */
```
again, don't use tab in source files, please enable showing special char in
your editor
##########
arch/arm/src/stm32u5/stm32_allocateheap.c:
##########
@@ -350,6 +357,26 @@ void arm_addregion(void)
#endif /* SRAM3 */
+#ifdef CONFIG_STM32U5_SRAM5_HEAP
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+
+ /* Allow user-mode access to the SRAM5 heap */
+
+ stm32_mpu_uheap((uintptr_t)SRAM5_START, STM32_SRAM5_SIZE);
+
+#endif
+
+ /* Colorize the heap for debug */
+
+ up_heap_color((void *)SRAM5_START, STM32_SRAM5_SIZE);
Review Comment:
remove the indent, only preprocess statement need the indent.
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -296,8 +343,14 @@ config STM32U5_DCMI_PSSI
bool "DCMI_PSSI"
default n
-config STM32U5_OTG
- bool "OTG"
+config STM32U5_OTGFS
+ bool "OTG FS"
+ depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX ||
STM32U5_STM32U575XX || STM32U5_STM32U585XX
Review Comment:
```suggestion
depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX ||
STM32U5_STM32U575XX || STM32U5_STM32U585XX
```
##########
boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c:
##########
@@ -0,0 +1,158 @@
+/****************************************************************************
+ * boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/mount.h>
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/input/buttons.h>
+#include <nuttx/leds/userled.h>
+#include <nuttx/spi/spi_transfer.h>
+#include <nuttx/board.h>
+#include <nuttx/clock.h>
+
+#include "nucleo-u5a5zj-q.h"
+
+#include <arch/board/board.h>
+
+#include <stm32_spi.h>
+
+#if defined(CONFIG_I2C)
+#include "stm32_i2c.h"
+FAR struct i2c_master_s *i2c1_m;
+FAR struct i2c_master_s *i2c2_m;
+#ifdef CONFIG_RTC_DSXXXX
+ #include <nuttx/timers/rtc.h>
+ #include <nuttx/timers/ds3231.h>
+#endif /* CONFIG_RTC_DSXXXX */
+
+#endif /* CONFIG_I2C */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define DEVNO_ZERO 0
+#define DEVNO_ONE 1
Review Comment:
no change
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -284,7 +275,63 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
+ default y
+
+config STM32U5_SRAM2
+ bool "SRAM2"
+ default n
+
+config STM32U5_SRAM3
+ bool "SRAM3"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+config STM32U5_SRAM5
+ bool "SRAM5"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+comment "SRAM Options"
+
+config STM32U5_SRAM2_HEAP
+ bool "SRAM2 is used for heap"
default n
+ depends on STM32U5_SRAM2
+ select STM32U5_SRAM2_INIT
+ ---help---
+ The STM32U5 SRAM2 region has special properties (power,
protection, parity)
+ which may be used by the application for special purposes. But
if these
+ special properties are not needed, it may be instead added to
the heap for
+ use by malloc().
+ NOTE: you must also select an appropriate number of memory
regions in the
+ 'Memory Management' section.
+
+config STM32U5_SRAM2_INIT
+ bool "SRAM2 is initialized to zero"
+ default n
+ depends on STM32U5_SRAM2
+ ---help---
+ The STM32U5 SRAM2 region has parity checking. However, when
the system
+ powers on, the memory is in an unknown state, and reads from
uninitialized
+ memory can trigger parity faults from the random data. This
can be
+ avoided by first writing to all locations to force the parity
into a valid
+ state.
+ However, if the SRAM2 is being used for it's battery-backed
capability,
+ this may be undesirable (because it will destroy the contents).
In that
+ case, the board should handle the initialization itself at the
appropriate
+ time.
+
+config STM32U5_SRAM3_HEAP
+ bool "SRAM3 is used for heap"
+ depends on STM32U5_SRAM3
+ default n
+
+config STM32U5_SRAM5_HEAP
+ bool "SRAM5 is used for heap"
+ depends on STM32U5_SRAM5
Review Comment:
```suggestion
depends on STM32U5_SRAM5
```
##########
arch/arm/src/stm32u5/stm32_allocateheap.c:
##########
@@ -350,6 +357,26 @@ void arm_addregion(void)
#endif /* SRAM3 */
+#ifdef CONFIG_STM32U5_SRAM5_HEAP
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+
+ /* Allow user-mode access to the SRAM5 heap */
+
+ stm32_mpu_uheap((uintptr_t)SRAM5_START, STM32_SRAM5_SIZE);
Review Comment:
```suggestion
stm32_mpu_uheap((uintptr_t)SRAM5_START, STM32_SRAM5_SIZE);
```
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -296,8 +343,14 @@ config STM32U5_DCMI_PSSI
bool "DCMI_PSSI"
default n
-config STM32U5_OTG
- bool "OTG"
+config STM32U5_OTGFS
+ bool "OTG FS"
+ depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX ||
STM32U5_STM32U575XX || STM32U5_STM32U585XX
+ default n
+
+config STM32U5_OTGHS
+ bool "OTG HS"
+ depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX
|| STM32U5_STM32U5A9XX
Review Comment:
```suggestion
depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX ||
STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
```
##########
boards/Kconfig:
##########
@@ -3114,7 +3114,7 @@ config ARCH_BOARD
default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1
default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A
default "b-u585i-iot02a" if ARCH_BOARD_B_U585I_IOT02A
- default "nucleo-u5a5zj-q" if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
+ default "nucleo-u5a5zj-q"
if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
Review Comment:
not fixed
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -284,7 +275,63 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
+ default y
+
+config STM32U5_SRAM2
+ bool "SRAM2"
+ default n
+
+config STM32U5_SRAM3
+ bool "SRAM3"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+config STM32U5_SRAM5
+ bool "SRAM5"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+comment "SRAM Options"
+
+config STM32U5_SRAM2_HEAP
+ bool "SRAM2 is used for heap"
default n
+ depends on STM32U5_SRAM2
+ select STM32U5_SRAM2_INIT
+ ---help---
+ The STM32U5 SRAM2 region has special properties (power,
protection, parity)
+ which may be used by the application for special purposes. But
if these
+ special properties are not needed, it may be instead added to
the heap for
+ use by malloc().
+ NOTE: you must also select an appropriate number of memory
regions in the
+ 'Memory Management' section.
+
+config STM32U5_SRAM2_INIT
+ bool "SRAM2 is initialized to zero"
+ default n
+ depends on STM32U5_SRAM2
Review Comment:
```suggestion
depends on STM32U5_SRAM2
```
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