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commit f1b6cf78da3aec1a45520302be5c902399467fef Author: hujun5 <[email protected]> AuthorDate: Wed Aug 16 19:01:19 2023 +0800 arch/arm: add CONFIG_ARCH_TRUSTZONE_SECURE to some code Signed-off-by: hujun5 <[email protected]> --- arch/arm/src/armv7-a/arm_gicv2.c | 4 ++++ arch/arm/src/armv7-r/arm_gicv2.c | 4 ++++ arch/arm64/src/common/arm64_gicv2.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index d5fb0dd555..0917ae700a 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -196,6 +196,7 @@ void arm_gic_initialize(void) /* Registers with 1-bit per interrupt */ +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE /* per-CPU inerrupts config: * ID0-ID7(SGI) for Non-secure interrupts * ID8-ID15(SGI) for Secure interrupts. @@ -203,6 +204,9 @@ void arm_gic_initialize(void) */ putreg32(0x000000ff, GIC_ICDISR(0)); +#else + putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */ +#endif putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */ /* Registers with 8-bits per interrupt */ diff --git a/arch/arm/src/armv7-r/arm_gicv2.c b/arch/arm/src/armv7-r/arm_gicv2.c index 83c56001e5..b5d5426697 100644 --- a/arch/arm/src/armv7-r/arm_gicv2.c +++ b/arch/arm/src/armv7-r/arm_gicv2.c @@ -196,6 +196,7 @@ void arm_gic_initialize(void) /* Registers with 1-bit per interrupt */ +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE /* per-CPU inerrupts config: * ID0-ID7(SGI) for Non-secure interrupts * ID8-ID15(SGI) for Secure interrupts. @@ -203,6 +204,9 @@ void arm_gic_initialize(void) */ putreg32(0x000000ff, GIC_ICDISR(0)); +#else + putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */ +#endif putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */ /* Registers with 8-bits per interrupt */ diff --git a/arch/arm64/src/common/arm64_gicv2.c b/arch/arm64/src/common/arm64_gicv2.c index de3127eca1..6a1227972a 100644 --- a/arch/arm64/src/common/arm64_gicv2.c +++ b/arch/arm64/src/common/arm64_gicv2.c @@ -922,6 +922,7 @@ static void arm_gic_initialize(void) /* Registers with 1-bit per interrupt */ +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE /* per-CPU inerrupts config: * ID0-ID7(SGI) for Non-secure interrupts * ID8-ID15(SGI) for Secure interrupts. @@ -929,6 +930,9 @@ static void arm_gic_initialize(void) */ putreg32(0x000000ff, GIC_ICDISR(0)); +#else + putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */ +#endif putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */ /* Registers with 8-bits per interrupt */
