jwfromm commented on a change in pull request #4644: [WIP] Relay op strategy URL: https://github.com/apache/incubator-tvm/pull/4644#discussion_r374966045
########## File path: python/tvm/relay/op/strategy/x86.py ########## @@ -0,0 +1,277 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +"""Definition of x86 operator strategy.""" +# pylint: disable=invalid-name,unused-argument,wildcard-import,unused-wildcard-import +from __future__ import absolute_import + +import logging + +import topi +from .generic import * +from .. import op as _op +from ....schedule import SpecializedCondition + +logger = logging.getLogger('strategy') + +@schedule_injective.register("cpu") +def schedule_injective_cpu(attrs, outs, target): + """schedule injective ops for x86""" + with target: + return topi.x86.schedule_injective(outs) + +@schedule_reduce.register("cpu") +def schedule_reduce_cpu(attrs, outs, target): + """schedule reduction ops for x86""" + with target: + return topi.x86.schedule_reduce(outs) + +@schedule_concatenate.register("cpu") +def schedule_concatenate_cpu(attrs, outs, target): + """schedule concatenate op for x86""" + with target: + return topi.x86.schedule_concatenate(outs) + +@schedule_pool.register("cpu") +def schedule_pool_cpu(attrs, outs, target): + """schedule pooling ops for x86""" + with target: + return topi.x86.schedule_pool(outs, attrs.layout) + +@schedule_adaptive_pool.register("cpu") +def schedule_adaptive_pool_cpu(attrs, outs, target): + """schedule adaptive pooling ops for x86""" + with target: + return topi.x86.schedule_adaptive_pool(outs) + +@schedule_softmax.register("cpu") +def schedule_softmax_cpu(attrs, outs, target): + """schedule softmax for x86""" + with target: + return topi.x86.schedule_softmax(outs) + +@conv2d_strategy.register("cpu") +def conv2d_strategy_cpu(attrs, inputs, out_type, target): + """conv2d x86 strategy""" + strategy = _op.OpStrategy() + data, kernel = inputs + dilation_h, dilation_w = get_const_tuple(attrs.dilation) + groups = attrs.groups + layout = attrs.data_layout + kernel_layout = attrs.kernel_layout + if dilation_h < 1 or dilation_w < 1: + raise ValueError("dilation should be positive value") + + if groups == 1: + if layout == "NCHW": + assert kernel_layout == "OIHW" + if topi.x86.is_int8_hw_support(data.dtype, kernel.dtype): + strategy.add_implement( + wrap_compute_conv2d(topi.x86.conv2d_nchw_int8), + wrap_topi_schedule(topi.x86.schedule_conv2d_nchw_int8)) + else: + strategy.add_implement( + wrap_compute_conv2d(topi.x86.conv2d_nchw), + wrap_topi_schedule(topi.x86.schedule_conv2d_nchw)) + elif layout == "NHWC": + assert kernel_layout == "HWIO" + logger.warning("For x86 target, NCHW layout is recommended for conv2d.") + strategy.add_implement( + wrap_compute_conv2d(topi.nn.conv2d_nhwc), + wrap_topi_schedule(topi.x86.schedule_conv2d_nhwc)) + elif layout == "HWCN": + assert kernel_layout == "HWIO" + logger.warning("For x86 target, NCHW layout is recommended for conv2d.") + strategy.add_implement( + wrap_compute_conv2d(topi.nn.conv2d_hwcn), + wrap_topi_schedule(topi.generic.schedule_conv2d_hwcn)) + else: + raise RuntimeError("Unsupported conv2d layout {} for cpu".format(layout)) + elif is_depthwise_conv2d(data.shape, layout, kernel.shape, kernel_layout, groups): + if layout == "NCHW": + assert kernel_layout == "OIHW" + channel_multiplier = get_const_tuple(inputs[1].shape)[1] + if channel_multiplier == 1: + strategy.add_implement( + wrap_compute_conv2d(topi.x86.depthwise_conv2d_nchw), + wrap_topi_schedule(topi.x86.schedule_depthwise_conv2d_nchw)) + else: + logger.warning("For x86 target, depthwise_conv2d with channel " + "multiplier greater than 1 is not optimized") + strategy.add_implement( + wrap_compute_conv2d(topi.nn.depthwise_conv2d_nchw), + wrap_topi_schedule(topi.generic.schedule_depthwise_conv2d_nchw)) + elif layout == "NHWC": + assert kernel_layout == "HWOI" + logger.warning("For x86 target, NCHW layout is recommended for depthwise_conv2d.") + strategy.add_implement( + wrap_compute_conv2d(topi.nn.depthwise_conv2d_nhwc), + wrap_topi_schedule(topi.generic.schedule_depthwise_conv2d_nhwc)) + else: + raise RuntimeError("Unsupported depthwise_conv2d layout {}".format(layout)) + else: # group_conv2d + if layout == 'NCHW': + assert kernel_layout == "OIHW" + logger.warning("group_conv2d is not optimized for cpu.") + strategy.add_implement( + wrap_compute_conv2d(topi.nn.group_conv2d_nchw, has_groups=True), + wrap_topi_schedule(topi.generic.schedule_group_conv2d_nchw)) + else: + raise RuntimeError("Unsupported group_conv2d layout {}".format(layout)) + return strategy + +@conv2d_NCHWc_strategy.register("cpu") +def conv2d_NCHWc_strategy_cpu(attrs, inputs, out_type, target): + """conv2d_NCHWc x86 strategy""" + strategy = _op.OpStrategy() + data, kernel = inputs + if topi.x86.is_int8_hw_support(data.dtype, kernel.dtype): + strategy.add_implement( + wrap_compute_conv2d(topi.x86.conv2d_NCHWc_int8, True, True), + wrap_topi_schedule(topi.x86.schedule_conv2d_NCHWc_int8)) + else: + strategy.add_implement( + wrap_compute_conv2d(topi.x86.conv2d_NCHWc, True, True), + wrap_topi_schedule(topi.x86.schedule_conv2d_NCHWc)) + return strategy + +@depthwise_conv2d_NCHWc_strategy.register("cpu") +def depthwise_conv2d_NCHWc_strategy_cpu(attrs, inputs, out_type, target): + """depthwise_conv2d x86 strategy""" + strategy = _op.OpStrategy() + strategy.add_implement( + wrap_compute_conv2d(topi.x86.depthwise_conv2d_NCHWc, True, True), + wrap_topi_schedule(topi.x86.schedule_depthwise_conv2d_NCHWc)) + return strategy + +@conv2d_transpose_strategy.register("cpu") +def conv2d_transpose_strategy_cpu(attrs, inputs, out_type, target): + """conv2d_transpose x86 strategy""" + layout = attrs.data_layout + dilation = get_const_tuple(attrs.dilation) + groups = attrs.groups + assert layout == "NCHW", "only support nchw for now" + assert dilation == (1, 1), "not support dilate now" + assert groups == 1, "only support groups == 1 for now" + strategy = _op.OpStrategy() + strategy.add_implement( + wrap_comptue_conv2d_transpose(topi.x86.conv2d_transpose_nchw), + wrap_topi_schedule(topi.x86.schedule_conv2d_transpose_nchw)) + return strategy + +@conv3d_strategy.register("cpu") +def conv3d_strategy_cpu(attrs, inputs, out_type, target): + """conv3d generic strategy""" + strategy = _op.OpStrategy() + layout = attrs.data_layout + if layout == "NCDHW": + logger.warning("conv3d with layout NCDHW is not optimized for cpu.") Review comment: Do you think it makes sense to add these log messages to the generic schedule function itself? The benefit would be not relying on them being manually added and removed when we add new backends or schedules with the downside of not being able to specify which device it's not optimized for. Given that the user is probably aware of what device they're running on, just saying "conv3d with layout NCHW is not optimized on this platform." might be plenty. ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: us...@infra.apache.org With regards, Apache Git Services
