Anndrey24 opened a new pull request, #16899:
URL: https://github.com/apache/tvm/pull/16899
This commit adds an `arm_cpu` conv2d NHWC schedule which generates SVE
instructions by extending the hybrid GeMM approach implemented in #16106 to use
scalable expressions as splitting factors.
Various vscale-related fixes needed to implement the schedule are also
included, such as:
- adding vscale bounds in the `ConstIntBoundAnalyzer` and
`IntervalSetEvaluator`
- simplifying `MinNode` and `MaxNode` that have scalable expression
operands in `RewriteSimplifier`, which would appear when defining the shape of
a buffer padded to be a multiple of vscale and in its respective buffer access
indices (e.g. `C_1 = T.Buffer((1024 * (T.vscale() * 16 + 256 - 16 % T.vscale()
* 16),), data=C)` instead of `C_1 = T.Buffer((1024 * (T.max(255, T.vscale() *
16 + 255 - 16 % T.vscale() * 16) + 1),), data=C)`)
The correctness of the new schedule is checked using a TOPI test, while the
presence of generated SVE instructions is verified by a codegen_aarch64 test.
The new rewrite_simplify rules are also covered by additional test cases.
cc @ekalda @lhutton1 @Lunderberg
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