This is an automated email from the ASF dual-hosted git repository.
tqchen pushed a commit to branch s-tir-s0
in repository https://gitbox.apache.org/repos/asf/tvm.git
The following commit(s) were added to refs/heads/s-tir-s0 by this push:
new 5a77ef8df4 fixes
5a77ef8df4 is described below
commit 5a77ef8df4dbe1f6fb8b38a28d067c4330aa935f
Author: tqchen <[email protected]>
AuthorDate: Wed Feb 4 14:50:04 2026 -0500
fixes
---
python/tvm/dlight/adreno/utils.py | 2 +-
python/tvm/dlight/base/common_schedules.py | 2 +-
python/tvm/exec/gpu_memory_bandwidth.py | 2 +-
python/tvm/meta_schedule/builder/local_builder.py | 2 +-
python/tvm/meta_schedule/testing/tune_te.py | 1 -
python/tvm/meta_schedule/testing/validate_database.py | 2 +-
python/tvm/meta_schedule/tune_context.py | 2 +-
python/tvm/relax/frontend/nn/llm/kv_cache.py | 2 +-
python/tvm/s_tir/__init__.py | 5 ++---
python/tvm/s_tir/pipeline.py | 2 --
python/tvm/s_tir/schedule/trace.py | 4 ++--
tests/python/meta_schedule/test_meta_schedule_mma_tensorize.py | 2 +-
.../meta_schedule/test_meta_schedule_postproc_rewrite_tensorize.py | 2 +-
13 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/python/tvm/dlight/adreno/utils.py
b/python/tvm/dlight/adreno/utils.py
index 0d2236ae5d..8f8d00d945 100644
--- a/python/tvm/dlight/adreno/utils.py
+++ b/python/tvm/dlight/adreno/utils.py
@@ -20,7 +20,7 @@
from typing import List
from tvm.target import Target
-from tvm import tir, s_tir
+from tvm import s_tir
from ..analysis import SBlockInfo
diff --git a/python/tvm/dlight/base/common_schedules.py
b/python/tvm/dlight/base/common_schedules.py
index 93805322f8..8e540e5457 100644
--- a/python/tvm/dlight/base/common_schedules.py
+++ b/python/tvm/dlight/base/common_schedules.py
@@ -17,7 +17,7 @@
"""Common schedule strategies for TIR."""
from typing import Callable, List
-from tvm import tir, s_tir
+from tvm import s_tir
from ..analysis import SBlockInfo
diff --git a/python/tvm/exec/gpu_memory_bandwidth.py
b/python/tvm/exec/gpu_memory_bandwidth.py
index 6ce28eb424..ff85d23b0f 100644
--- a/python/tvm/exec/gpu_memory_bandwidth.py
+++ b/python/tvm/exec/gpu_memory_bandwidth.py
@@ -21,7 +21,7 @@ import itertools
import numpy as np
import tvm
-from tvm import te, tir
+from tvm import te
from tvm.meta_schedule.runner import EvaluatorConfig, RPCConfig
from tvm.testing import local_run, rpc_run
diff --git a/python/tvm/meta_schedule/builder/local_builder.py
b/python/tvm/meta_schedule/builder/local_builder.py
index c5d8b21d89..a00c674af1 100644
--- a/python/tvm/meta_schedule/builder/local_builder.py
+++ b/python/tvm/meta_schedule/builder/local_builder.py
@@ -254,7 +254,7 @@ def default_build(mod: IRModule, target: Target, _params:
Optional[Dict[str, Ten
"""
# pylint: disable=import-outside-toplevel
from tvm.driver import build as tvm_build
- import tvm.tir.tensor_intrin # pylint: disable=unused-import
+ import tvm.s_tir.tensor_intrin # pylint: disable=unused-import
from tvm.tir.transform import RemoveWeightLayoutRewriteBlock
# pylint: enable=import-outside-toplevel
diff --git a/python/tvm/meta_schedule/testing/tune_te.py
b/python/tvm/meta_schedule/testing/tune_te.py
index 983e2140cf..3d907baebf 100644
--- a/python/tvm/meta_schedule/testing/tune_te.py
+++ b/python/tvm/meta_schedule/testing/tune_te.py
@@ -21,7 +21,6 @@ from typing import Optional
import tvm
from tvm import meta_schedule as ms
-from tvm import tir
from tvm.meta_schedule.testing.te_workload import create_te_workload
from tvm.support import describe
from tvm.testing.utils import strtobool
diff --git a/python/tvm/meta_schedule/testing/validate_database.py
b/python/tvm/meta_schedule/testing/validate_database.py
index 5c7253e96f..38e78230e0 100644
--- a/python/tvm/meta_schedule/testing/validate_database.py
+++ b/python/tvm/meta_schedule/testing/validate_database.py
@@ -34,7 +34,7 @@ from tvm.s_tir import Schedule
from tvm.s_tir.schedule import Trace
from tvm.meta_schedule.utils import remove_build_dir
from tvm.meta_schedule.testing.tune_utils import generate_input_data
-from tvm.tir.tensor_intrin import * # type: ignore # pylint:
disable=wildcard-import,unused-wildcard-import
+from tvm.s_tir.tensor_intrin import * # type: ignore # pylint:
disable=wildcard-import,unused-wildcard-import
from tvm.testing.utils import strtobool
DELIMITOR = "\n" + "-" * 30 + "\n"
diff --git a/python/tvm/meta_schedule/tune_context.py
b/python/tvm/meta_schedule/tune_context.py
index 9b651360e7..ac7fa36c52 100644
--- a/python/tvm/meta_schedule/tune_context.py
+++ b/python/tvm/meta_schedule/tune_context.py
@@ -107,7 +107,7 @@ class TuneContext(Object):
logger: Optional[Logger] = None,
):
# pylint: disable=import-outside-toplevel
- import tvm.tir.tensor_intrin # pylint: disable=unused-import
+ import tvm.s_tir.tensor_intrin # pylint: disable=unused-import
from .search_strategy import SearchStrategy
from .space_generator import SpaceGenerator
diff --git a/python/tvm/relax/frontend/nn/llm/kv_cache.py
b/python/tvm/relax/frontend/nn/llm/kv_cache.py
index 8f45a92475..4d3ce0cbc4 100644
--- a/python/tvm/relax/frontend/nn/llm/kv_cache.py
+++ b/python/tvm/relax/frontend/nn/llm/kv_cache.py
@@ -24,7 +24,7 @@ from typing import Any, Dict, List, Literal, Optional, Tuple,
Union
import tvm
from tvm import relax as rx
-from tvm import tir
+from tvm import tir, s_tir
from tvm.relax.frontend.nn import Object, Tensor
from tvm.runtime import DataType
from tvm.script import tir as T
diff --git a/python/tvm/s_tir/__init__.py b/python/tvm/s_tir/__init__.py
index e28f031c7b..287575c85b 100644
--- a/python/tvm/s_tir/__init__.py
+++ b/python/tvm/s_tir/__init__.py
@@ -17,11 +17,10 @@
# pylint: disable=invalid-name
"""S-TIR namespace for scheduable TensorIR"""
+from tvm.tir.function import TensorIntrin
+
from . import backend
from . import pipeline
from . import schedule
-
-from tvm.tir.function import TensorIntrin
-
from .schedule import StmtSRef, SBlockScope, ScheduleState, Schedule,
ScheduleError, Trace
from .block_dependence_info import SBlockDependenceInfo
diff --git a/python/tvm/s_tir/pipeline.py b/python/tvm/s_tir/pipeline.py
index e1b404b421..ce9e8add62 100644
--- a/python/tvm/s_tir/pipeline.py
+++ b/python/tvm/s_tir/pipeline.py
@@ -21,8 +21,6 @@
import tvm
from tvm import tir
from tvm.tir import pipeline as tir_pipeline
-from . import backend
-
def default_s_tir_pipeline():
"""The default tir pipeline used in tvm.tir.build"""
diff --git a/python/tvm/s_tir/schedule/trace.py
b/python/tvm/s_tir/schedule/trace.py
index db4ec13489..5796b7a225 100644
--- a/python/tvm/s_tir/schedule/trace.py
+++ b/python/tvm/s_tir/schedule/trace.py
@@ -20,10 +20,10 @@ from typing import TYPE_CHECKING, Any, Callable, Dict,
List, Optional
from tvm_ffi import register_object as _register_object
from tvm.runtime import Object
-
-from ...ir import Array, Map, save_json
from tvm.tir.expr import FloatImm, IntImm
from tvm.tir.function import IndexMap
+
+from ...ir import Array, Map, save_json
from . import _ffi_api
from .instruction import ATTR_TYPE, INPUT_RV_TYPE, Instruction
diff --git a/tests/python/meta_schedule/test_meta_schedule_mma_tensorize.py
b/tests/python/meta_schedule/test_meta_schedule_mma_tensorize.py
index ccf6e3e972..d842a64645 100644
--- a/tests/python/meta_schedule/test_meta_schedule_mma_tensorize.py
+++ b/tests/python/meta_schedule/test_meta_schedule_mma_tensorize.py
@@ -19,7 +19,7 @@ import tvm
import numpy as np
from tvm.script import tir as T
from tvm.s_tir.schedule import Schedule
-import tvm.tir.tensor_intrin # pylint: disable=unused-import
+import tvm.s_tir.tensor_intrin # pylint: disable=unused-import
import tvm.testing
import pytest
diff --git
a/tests/python/meta_schedule/test_meta_schedule_postproc_rewrite_tensorize.py
b/tests/python/meta_schedule/test_meta_schedule_postproc_rewrite_tensorize.py
index 7512b27d8e..f93e837020 100644
---
a/tests/python/meta_schedule/test_meta_schedule_postproc_rewrite_tensorize.py
+++
b/tests/python/meta_schedule/test_meta_schedule_postproc_rewrite_tensorize.py
@@ -18,7 +18,7 @@
import tvm
from tvm import meta_schedule as ms
from tvm.script import tir as T
-from tvm.tir.tensor_intrin import cuda, rocm, x86
+from tvm.s_tir.tensor_intrin import cuda, rocm, x86
@tvm.script.ir_module
