This is an automated email from the ASF dual-hosted git repository.
MasterJH5574 pushed a change to branch v0.27.0
in repository https://gitbox.apache.org/repos/asf/tvm.git
from fa3a688fb2 [FIX] Update v0.27.0 versions and FFI floor (#20390)
add df3085d315 [REFACTOR][IR] Promote primitive bitwise and shift
operations to nodes (#20392)
add ade6137149 [FIX][TIRx] Avoid stale constraints from mutable memory
predicates (#20393)
add be5a0d8d5d [TIRx][CUDA] Preserve kernel launch calls and add CUDA host
source bundling (#20395)
add adf6523934 [Fix][Metal][WebGPU] Preserve variable bindings when
resolving allocation bounds (#20337)
add 527618afbf [Fix][Relax] Allow callers to specify scan index-width
budget (#20336)
add abe90e3ffa [REFACTOR][TIRx] Group buffer APIs and remove generic
composition (#20402)
No new revisions were added by this update.
Summary of changes:
docs/tirx/api/tile.rst | 4 -
docs/tirx/api/tirx.rst | 5 +
docs/tirx/tile_primitives.rst | 3 +-
include/tvm/ir/expr_functor.h | 36 ++
include/tvm/ir/prim/builtin.h | 18 -
include/tvm/ir/prim/expr.h | 126 +++++++
include/tvm/relax/expr_functor.h | 24 ++
include/tvm/te/operation.h | 2 +-
include/tvm/tirx/attrs.h | 73 ++++
include/tvm/tirx/buffer_region.h | 58 ---
include/tvm/tirx/builtin.h | 18 +
include/tvm/tirx/{buffer.h => expr.h} | 149 +-------
include/tvm/tirx/function.h | 2 +-
include/tvm/tirx/script/builder/frame.h | 31 --
include/tvm/tirx/script/builder/ir.h | 11 -
include/tvm/tirx/stmt.h | 3 +-
include/tvm/tirx/tile_primitive.h | 2 -
include/tvm/tirx/type.h | 150 ++++++++
python/tvm/backend/cuda/__init__.py | 3 +
python/tvm/backend/cuda/host.py | 78 ++++
.../backend/cuda/tile_primitive/copy_async/tma.py | 17 +-
.../trn/tile_primitive/compose_op/__init__.py | 1 -
.../trn/tile_primitive/compose_op/compose_op.py | 47 ---
python/tvm/ir/prim/__init__.py | 6 +
python/tvm/ir/prim/expr.py | 119 ++++++
python/tvm/relax/backend/dispatch_sort_scan.py | 31 +-
python/tvm/relax/expr_functor.py | 30 ++
python/tvm/tirx/__init__.py | 2 +
python/tvm/tirx/build.py | 2 +-
python/tvm/tirx/expr.py | 6 +
python/tvm/tirx/op.py | 84 +++++
python/tvm/tirx/operator/tile_primitive/ops.py | 25 --
python/tvm/tirx/script/builder/frame.py | 4 -
python/tvm/tirx/script/builder/ir.py | 16 +
python/tvm/tirx/script/builder/tirx.py | 24 +-
python/tvm/tirx/script/tile.py | 4 -
src/backend/cuda/codegen/codegen_cuda_host.cc | 401 +++++++++++++++++++++
src/backend/cuda/codegen/target_kind.cc | 2 +
src/backend/metal/codegen/codegen_metal.cc | 11 +-
src/backend/metal/codegen/codegen_metal.h | 2 +
src/backend/vulkan/codegen/codegen_spirv.cc | 72 ++--
src/backend/vulkan/codegen/codegen_spirv.h | 6 +
src/backend/webgpu/codegen/codegen_webgpu.cc | 43 ++-
src/backend/webgpu/codegen/codegen_webgpu.h | 5 +
src/ir/expr_functor.cc | 66 ++++
src/ir/prim/builtin.cc | 24 --
src/ir/prim/deep_equal.cc | 11 +
src/ir/prim/expr.cc | 166 +++++++++
src/ir/prim/op.cc | 12 +-
src/relax/backend/vm/codegen_vm_tir.cc | 6 +
src/relax/ir/expr_functor.cc | 21 ++
src/relax/transform/compute_prim_value.cc | 6 +
src/s_tir/analysis/estimate_flops.cc | 26 ++
src/s_tir/analysis/identify_memcpy.cc | 2 +-
.../feature_extractor/per_store_feature.cc | 6 +
src/s_tir/schedule/ir_comparator.cc | 11 +
src/s_tir/schedule/ir_comparator.h | 6 +
src/s_tir/transform/lower_async_dma.cc | 2 +-
src/s_tir/transform/rewrite_unsafe_select.cc | 6 +
src/sym/const_int_bound.cc | 33 +-
src/sym/constraint_helpers.h | 16 +-
src/sym/modular_set.cc | 34 +-
src/sym/pattern_match.h | 90 +++--
src/sym/rewrite_simplify.cc | 34 +-
src/sym/rewrite_simplify.h | 2 +
src/sym/z3_prover.cc | 71 ++--
src/target/intrin_rule.cc | 2 +-
src/target/llvm/codegen_llvm.cc | 44 ++-
src/target/llvm/codegen_llvm.h | 6 +
src/target/source/codegen_c.cc | 52 ++-
src/target/source/codegen_c.h | 62 ++--
src/tirx/analysis/filter_canonical.cc | 22 +-
src/tirx/analysis/filter_canonical.h | 2 +-
src/tirx/ir/buffer.cc | 244 +++++--------
src/tirx/ir/buffer_load.cc | 2 +-
src/tirx/ir/data_type_rewriter.cc | 85 +++--
src/tirx/ir/data_type_rewriter.h | 6 +
src/tirx/ir/ir_mutator_with_analyzer.cc | 19 +-
src/tirx/ir/specialize.cc | 10 +-
src/tirx/ir/stmt.cc | 120 ------
src/tirx/ir/tir_visitor_with_path.cc | 10 +
src/tirx/ir/tir_visitor_with_path.h | 6 +
src/tirx/ir/type.cc | 196 ++++++++++
src/tirx/op/builtin.cc | 38 +-
src/tirx/op/tirx.cc | 1 -
src/tirx/script/builder/frame.cc | 14 -
src/tirx/script/builder/ir.cc | 11 -
src/tirx/script/printer/expr.cc | 53 +++
src/tirx/script/printer/stmt.cc | 87 ++---
src/tirx/script/printer/utils.h | 2 +-
src/tirx/transform/common_subexpr_elim.cc | 10 +
src/tirx/transform/lower_intrin.cc | 2 +-
src/tirx/transform/lower_tirx_dedup_tensormap.cc | 50 ++-
src/tirx/transform/lower_tvm_builtin.cc | 35 +-
src/tirx/transform/make_packed_api.cc | 2 +-
src/tirx/transform/split_host_device.cc | 6 +-
src/tirx/transform/tile_primitive_dispatch.cc | 55 ++-
src/tirx/transform/tvm_ffi_binder.h | 2 +-
src/tirx/transform/vectorize_loop.cc | 26 +-
tests/cpp/sym_simplify_test.cc | 2 +-
tests/cpp/tir_analysis_side_effect.cc | 2 +-
tests/python/codegen/test_target_codegen_cuda.py | 41 +++
tests/python/codegen/test_target_codegen_metal.py | 79 +++-
tests/python/codegen/test_target_codegen_webgpu.py | 110 ++++++
.../relax/test_backend_dispatch_sort_scan.py | 46 ++-
tests/python/sym/test_sym_rewrite_simplify.py | 2 +-
tests/python/tirx-base/test_tir_nodes.py | 22 +-
tests/python/tirx-base/test_tir_op_types.py | 12 +-
.../test_tir_transform_lower_tvm_builtin.py | 10 +-
.../tirx-transform/test_tir_transform_simplify.py | 46 +++
.../test_tir_transform_split_host_device.py | 23 +-
.../tirx-transform/test_tir_transform_vectorize.py | 5 +-
.../operator/tile_primitive/cuda/copy/test_reg.py | 22 +-
.../tile_primitive/cuda/copy_async/test_tma.py | 32 +-
.../operator/tile_primitive/test_dispatcher.py | 16 +-
tests/python/tirx/test_layout.py | 22 +-
tests/python/tirx/test_op_namespace_cleanup.py | 1 -
tests/python/tirx/test_parser_printer.py | 54 ---
118 files changed, 2926 insertions(+), 1310 deletions(-)
create mode 100644 include/tvm/tirx/attrs.h
delete mode 100644 include/tvm/tirx/buffer_region.h
rename include/tvm/tirx/{buffer.h => expr.h} (68%)
create mode 100644 python/tvm/backend/cuda/host.py
delete mode 100644
python/tvm/backend/trn/tile_primitive/compose_op/compose_op.py
create mode 100644 src/backend/cuda/codegen/codegen_cuda_host.cc
