This is an automated email from the ASF dual-hosted git repository.
tqchen pushed a change to branch manylinux-ci-836
in repository https://gitbox.apache.org/repos/asf/tvm-tirx.git
discard 89916b44e [BUILD] Use the current LLVM and Z3 SDK releases
discard 08abefff0 [CI] Use the CUDA driver stubs provided by manylinux images
discard b9da34d2d [FEAT] Enable SPIR-V code generation independently of Vulkan
runtime
discard 5063c5014 [CI] Pin Doxygen to preserve Breathe function-pointer parsing
discard 833a6f5f1 [CI] Build documentation in manylinux with explicit Doxygen
bootstrap
discard 9e03b67c9 [CI] Provide CUDA driver link stubs to host-bundle tests
discard 1c3894ef7 [FIX] Scope negation pattern variables to their rewrite paths
discard e82bde32c [FIX] Value-initialize negation rewrite pattern variables
discard aa8bbc2d5 Use stock manylinux images for CPU and CUDA CI
add c20448f23 Remove blanket MSVC warning disables and fix narrowing
conversions (#59)
add 77e9059d8 [FIX] Restrict Ramp elements to 32-bit and 64-bit integers
(#64)
add 4f57008f3 [FIX] Preserve offsets when sharing iterator padding (#65)
add 13d57030f [FIX] Lower scalar fmod through the default intrinsic rule
(#66)
add 1d9375b20 [REFACTOR] Synchronize analyzers from constraint contexts
(#67)
add 7bcc2e51c [FEAT] Infer constant bounds from affine predicates (#69)
add 642ff3fc7 [FIX][CUDA] Correct vector storage, alignment, and FP8 casts
(#68)
add 7ec946256 [FEAT][RUST] Generate TVMScript builders for registered
operators (#58)
add 902081f43 [REFACTOR][TIRx] Analyze vectorization eligibility before
rewriting (#70)
add abb9dae08 [FEAT] Split LLVM code generation into configurable backend
libraries (#72)
add 7b2bc5834 [SYM] Document Analyzer contracts and narrow internal DLL
exports (#73)
add 93e16e774 [FIX] Avoid collection and invalid-reference warnings in
tests (#71)
add d4106ba04 [FIX] Keep optional LLVM wheel companion libraries external
(#74)
add 7c0d37abf [DOCS] Rework the IR Walkthrough around a shared TVMScript
program (#62)
add 949e857d3 Reduce wheel size with section GC and direct LLVM pipelines
(#75)
new 7f7884abb Use stock manylinux images for CPU and CUDA CI
new b95fc5bc2 [FIX] Value-initialize negation rewrite pattern variables
new c879bbd3b [FIX] Scope negation pattern variables to their rewrite paths
new d2d71f121 [CI] Provide CUDA driver link stubs to host-bundle tests
new 7bee83a7d [CI] Build documentation in manylinux with explicit Doxygen
bootstrap
new 3e354eec7 [CI] Pin Doxygen to preserve Breathe function-pointer parsing
new 3e62b5858 [FEAT] Enable SPIR-V code generation independently of Vulkan
runtime
new 0519ba0ad [CI] Use the CUDA driver stubs provided by manylinux images
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Summary of changes:
.github/actions/build-wheel-for-publish/action.yml | 48 +-
.github/workflows/publish_wheel.yml | 73 +-
3rdparty/tvm-ffi | 2 +-
CMakeLists.txt | 12 +-
ci/wheel/check_llvm_targets_wheel.py | 64 +
ci/wheel/prepare_release_metadata.py | 67 ++
ci/wheel/tvm-tirx-llvm-targets/CMakeLists.txt | 32 +
ci/wheel/tvm-tirx-llvm-targets/pyproject.toml | 72 ++
.../python/tvm_tirx_llvm_targets/__init__.py | 25 +-
cmake/modules/LLVM.cmake | 60 +-
cmake/utils/Library.cmake | 10 +
docs/get_started/example.rst | 59 +
.../get_started/examples/add_one_cpu.py | 39 +-
.../get_started/examples/add_one_cuda.py | 41 +-
docs/index.rst | 7 +
docs/ir/examples/operators_and_calls.py | 56 -
docs/ir/examples/printing_and_parsing.py | 132 --
docs/ir/examples/sigmoid.py | 217 ++++
docs/ir/examples/statements_and_functions.py | 78 --
docs/ir/examples/tvmscript_sigmoid.py | 87 ++
docs/ir/examples/types_and_expressions.py | 100 --
docs/ir/functions_and_modules.rst | 129 +-
docs/ir/operators_and_calls.rst | 183 ++-
docs/ir/overview.rst | 118 +-
docs/ir/printing_and_parsing.rst | 159 +--
docs/ir/statements.rst | 164 ++-
docs/ir/types_and_expressions.rst | 387 +++---
docs/reference/python/sym.rst | 1 -
docs/reference/python/tirx.script.rst | 1 +
include/tvm/ir/prim/vector_expr.h | 5 +-
include/tvm/ir/scope_stack.h | 9 +-
include/tvm/ir/with_context.h | 8 +-
include/tvm/sym/analyzer.h | 661 +++++-----
include/tvm/sym/constraint.h | 46 +-
include/tvm/tirx/stmt_functor_with_analyzer.h | 175 ---
.../tirx/stmt_functor_with_constraint_context.h | 24 +-
pyproject.toml | 7 +-
.../tvm_tirx/backend/cuda/tile/patterns/common.py | 16 +-
python/tvm_tirx/backend/cuda/tile/patterns/mma.py | 2 +-
.../backend/cuda/tile/patterns/tcgen05_mma.py | 2 +-
python/tvm_tirx/backend/cuda/tile/patterns/tma.py | 2 +-
python/tvm_tirx/backend/cuda/tile/patterns/tmem.py | 4 +-
python/tvm_tirx/backend/trn/tile/common.py | 6 +-
python/tvm_tirx/base.py | 49 +
python/tvm_tirx/ir/prim/vector_expr.py | 6 +-
python/tvm_tirx/support/popen_worker.py | 6 +-
python/tvm_tirx/sym/analyzer.py | 113 +-
python/tvm_tirx/tirx/script/ir_builder/op.py | 66 +
python/tvm_tirx/tirx/transform/transform.py | 6 +
rust/examples/define_ops.rs | 9 +-
rust/src/ir/op_def.rs | 9 +-
rust/src/lib.rs | 7 +-
rust/src/sym/analyzer.rs | 117 +-
rust/tests/sym/analyzer.rs | 29 +-
rust/tests/sym/main.rs | 35 +-
src/backend/cuda/codegen/codegen_cuda.cc | 71 +-
src/backend/cuda/codegen/codegen_cuda.h | 3 +
src/backend/cuda/codegen/cuda_fallback_module.cc | 9 +-
src/backend/cuda/codegen/cuda_fallback_module.h | 12 +-
src/backend/cuda/launch/launch_plan.h | 2 +-
src/backend/cuda/transform/lower_iket.cc | 4 +-
.../hexagon/codegen/hexagon_fallback_module.cc | 8 +-
.../hexagon/codegen/hexagon_fallback_module.h | 13 +-
.../hexagon/codegen/llvm/codegen_hexagon.cc | 12 +-
.../hexagon/codegen/llvm/intrin_rule_hexagon.cc | 6 +-
src/backend/hexagon/codegen/target_kind.cc | 16 -
src/backend/metal/codegen/codegen_metal.cc | 6 +-
src/backend/rocm/codegen/llvm/codegen_amdgpu.cc | 6 +-
src/backend/rocm/codegen/llvm/intrin_rule_rocm.cc | 2 +-
src/backend/rocm/codegen/rocm_fallback_module.cc | 9 +-
src/backend/rocm/codegen/rocm_fallback_module.h | 12 +-
src/backend/rocm/codegen/target_kind.cc | 12 -
src/backend/trn/transform/lower_trainium_layout.cc | 56 +-
src/backend/vulkan/codegen/codegen_spirv.cc | 29 +-
src/backend/webgpu/codegen/codegen_webgpu.cc | 12 +-
src/codegen/canonicalizer/arm_mprofile.cc | 10 +
src/codegen/intrin_rule.cc | 3 +
src/codegen/llvm/canonicalizer/arm_aprofile.cc | 28 +
src/codegen/llvm/canonicalizer/canonicalize.cc | 21 +-
src/codegen/llvm/codegen_cpu.cc | 6 +-
src/codegen/llvm/codegen_llvm.cc | 108 +-
src/codegen/llvm/codegen_llvm.h | 2 +-
src/codegen/llvm/codegen_x86_64.cc | 8 +-
src/codegen/llvm/llvm_instance.cc | 16 +-
src/ir/prim/op.cc | 3 +-
src/ir/prim/vector_expr.cc | 12 +-
src/runtime/logging.cc | 8 +-
src/runtime/thread_pool.cc | 6 +-
src/runtime/threading_backend.cc | 2 +-
src/script/ir_builder/ir.cc | 2 +-
src/script/printer/doc_printer.cc | 6 +-
src/sym/analyzer.cc | 281 +++--
src/sym/canonical_simplify.cc | 11 +-
src/sym/const_int_bound.cc | 164 ++-
src/sym/constraint_helpers.h | 44 +-
src/sym/int_set.cc | 103 +-
src/sym/iter_affine_map.cc | 86 +-
src/sym/known_comparison_analyzer.cc | 69 +-
src/sym/modular_set.cc | 85 +-
src/sym/rewrite_simplify.cc | 66 +-
src/sym/rewrite_simplify.h | 12 +-
src/sym/simplify_base.cc | 61 +-
src/sym/simplify_base.h | 1 -
src/sym/z3_prover.cc | 445 +++----
src/tirx/ir/data_type_rewriter.cc | 7 +-
src/tirx/ir/index_map.cc | 6 +-
src/tirx/ir/ir_mutator_with_analyzer.cc | 362 ------
src/tirx/ir/ir_visitor_with_analyzer.cc | 140 ---
src/tirx/ir/layout/layout.cc | 1 +
src/tirx/ir/layout/utils.cc | 2 +-
.../ir/stmt_functor_with_constraint_context.cc | 64 +
src/tirx/ir/structural_constraints.cc | 119 +-
src/tirx/ir/transform.cc | 1 -
src/tirx/transform/flatten_tensor.cc | 29 +-
src/tirx/transform/lower_intrin.cc | 54 +-
src/tirx/transform/lower_tensor_layouts.cc | 56 +-
src/tirx/transform/lower_thread_allreduce.cc | 12 +-
src/tirx/transform/narrow_datatype.cc | 32 +-
src/tirx/transform/remove_no_op.cc | 46 +-
src/tirx/transform/renormalize_split_pattern.cc | 23 +-
src/tirx/transform/split_host_device.cc | 2 +-
src/tirx/transform/stmt_simplify.cc | 46 +-
src/tirx/transform/tvm_ffi_binder.cc | 6 +-
src/tirx/transform/vectorize_loop.cc | 1267 +++++---------------
...ructural_mutate_with_constraint_context_test.cc | 2 +-
...tructural_visit_with_constraint_context_test.cc | 2 +-
tests/python/backend/cuda/codegen/test_fp8.py | 20 +
.../backend/cuda/codegen/test_vector_storage.py | 62 +
tests/python/codegen/gpu_common/test_intrinsics.py | 5 +-
tests/python/codegen/llvm/test_arm.py | 6 +-
tests/python/codegen/llvm/test_basic.py | 4 +-
tests/python/codegen/llvm/test_riscv.py | 22 +-
tests/python/ir/test_op_rust.py | 33 +-
tests/python/sym/test_analyzer_object.py | 129 +-
tests/python/sym/test_canonical_simplify.py | 102 +-
tests/python/sym/test_const_int_bound.py | 58 +-
tests/python/sym/test_intset.py | 24 +-
tests/python/sym/test_iter_affine_map.py | 68 +-
tests/python/sym/test_modular_set.py | 81 +-
tests/python/sym/test_rewrite_simplify.py | 32 +-
tests/python/sym/test_simplify.py | 43 +-
tests/python/sym/test_z3.py | 231 +++-
tests/python/tirx/base/test_index_map.py | 30 +-
tests/python/tirx/base/test_intrin.py | 16 +-
tests/python/tirx/script/test_expose_script_op.py | 92 ++
...st_structural_mutate_with_constraint_context.py | 2 +-
...est_structural_visit_with_constraint_context.py | 2 +-
tests/python/tirx/transform/test_bf16_legalize.py | 4 +-
tests/python/tirx/transform/test_simplify.py | 2 +-
tests/python/tirx/transform/test_tile_dispatch.py | 2 +-
tests/python/tirx/transform/test_vectorize.py | 453 ++-----
151 files changed, 4796 insertions(+), 4817 deletions(-)
create mode 100644 ci/wheel/check_llvm_targets_wheel.py
create mode 100644 ci/wheel/prepare_release_metadata.py
create mode 100644 ci/wheel/tvm-tirx-llvm-targets/CMakeLists.txt
create mode 100644 ci/wheel/tvm-tirx-llvm-targets/pyproject.toml
copy tests/python/tirx/tile/cuda/conftest.py =>
ci/wheel/tvm-tirx-llvm-targets/python/tvm_tirx_llvm_targets/__init__.py (63%)
create mode 100644 docs/get_started/example.rst
copy python/tvm_tirx/tirx/tile/common.py =>
docs/get_started/examples/add_one_cpu.py (58%)
copy tests/python/tirx/transform/test_decorate_device_scope.py =>
docs/get_started/examples/add_one_cuda.py (53%)
delete mode 100644 docs/ir/examples/operators_and_calls.py
delete mode 100644 docs/ir/examples/printing_and_parsing.py
create mode 100644 docs/ir/examples/sigmoid.py
delete mode 100644 docs/ir/examples/statements_and_functions.py
create mode 100644 docs/ir/examples/tvmscript_sigmoid.py
delete mode 100644 docs/ir/examples/types_and_expressions.py
delete mode 100644 include/tvm/tirx/stmt_functor_with_analyzer.h
delete mode 100644 src/tirx/ir/ir_mutator_with_analyzer.cc
delete mode 100644 src/tirx/ir/ir_visitor_with_analyzer.cc
create mode 100644 tests/python/backend/cuda/codegen/test_vector_storage.py
create mode 100644 tests/python/tirx/script/test_expose_script_op.py
