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The following commit(s) were added to refs/heads/master by this push: new 22e4b88 [Hardware][Xilinx] utilize uram (#6) 22e4b88 is described below commit 22e4b88060d26cc4c309cbbbf6fba66770c20e5b Author: ZHANG Hao <zhanghao...@gmail.com> AuthorDate: Wed Apr 29 23:57:04 2020 +0800 [Hardware][Xilinx] utilize uram (#6) Co-authored-by: Zhang Hao <zhang...@4paradigm.com> --- config/vta_config.py | 8 ++++++++ hardware/xilinx/scripts/vivado.tcl | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/config/vta_config.py b/config/vta_config.py index 9bb6d7b..d7ea0df 100644 --- a/config/vta_config.py +++ b/config/vta_config.py @@ -79,6 +79,8 @@ def main(): help="returns output memory depth") parser.add_argument("--get-out-mem-axi-ratio", action="store_true", help="returns ratio between output element width and axi width") + parser.add_argument("--get-num-wgt-mem-uram", action="store_true", + help="returns number of weight memory blocks to be implemented on URAM") parser.add_argument("--get-axi-cache-bits", action="store_true", help="returns AXI system ARCACHE/AWCACHE hardcoded bit value") parser.add_argument("--get-axi-prot-bits", action="store_true", @@ -193,6 +195,12 @@ def main(): if args.get_out_mem_axi_ratio: print(pkg.out_mem_axi_ratio) + if args.get_num_wgt_mem_uram: + if hasattr(pkg, 'num_wgt_mem_uram'): + print(pkg.num_wgt_mem_uram) + else: + print(0) + if args.get_axi_cache_bits: print(pkg.axi_cache_bits) diff --git a/hardware/xilinx/scripts/vivado.tcl b/hardware/xilinx/scripts/vivado.tcl index 1f8f1da..2ed0733 100644 --- a/hardware/xilinx/scripts/vivado.tcl +++ b/hardware/xilinx/scripts/vivado.tcl @@ -50,6 +50,7 @@ set wgt_mem_depth [exec python $vta_config --get-wgt-mem-depth] set out_part [exec python $vta_config --get-out-mem-banks] set out_mem_width [exec python $vta_config --get-out-mem-width] set out_mem_depth [exec python $vta_config --get-out-mem-depth] +set num_wgt_mem_uram [exec python $vta_config --get-num-wgt-mem-uram] # AXI bus signals set axi_cache [exec python $vta_config --get-axi-cache-bits] @@ -247,6 +248,9 @@ for {set i 0} {$i < $wgt_part} {incr i} { connect_bd_intf_net -intf_net compute_0_wgt_mem_${i}_V_PORTA \ [get_bd_intf_pins $wgt_mem/BRAM_PORTB] \ $portb + if { $device_family eq "zynq-ultrascale+" && $i < $num_wgt_mem_uram } { + set_property -dict [list CONFIG.PRIM_type_to_Implement {URAM}] $wgt_mem + } } # Create and connect out_mem partitions