aasorokiin commented on a change in pull request #32:
URL: https://github.com/apache/tvm-vta/pull/32#discussion_r692642018
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File path: hardware/chisel/src/main/resources/verilog/VTAMemDPI.v
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@@ -18,89 +18,153 @@
*/
module VTAMemDPI #
-( parameter LEN_BITS = 8,
- parameter ADDR_BITS = 64,
- parameter DATA_BITS = 64
-)
-(
- input clock,
- input reset,
- input dpi_req_valid,
- input dpi_req_opcode,
- input [LEN_BITS-1:0] dpi_req_len,
- input [ADDR_BITS-1:0] dpi_req_addr,
- input dpi_wr_valid,
- input [DATA_BITS-1:0] dpi_wr_bits,
- output logic dpi_rd_valid,
- output logic [DATA_BITS-1:0] dpi_rd_bits,
- input dpi_rd_ready
-);
+ ( parameter LEN_BITS = 8,
+ parameter ADDR_BITS = 64,
+ parameter DATA_BITS = 64,
+ parameter STRB_BITS = DATA_BITS/8
+ )
+ (
+ input clock,
+ input reset,
+ input dpi_req_ar_valid,
+ input [LEN_BITS-1:0] dpi_req_ar_len,
+ input [7:0] dpi_req_ar_id,
+ input [ADDR_BITS-1:0] dpi_req_ar_addr,
+ input dpi_req_aw_valid,
+ input [LEN_BITS-1:0] dpi_req_aw_len,
+ input [ADDR_BITS-1:0] dpi_req_aw_addr,
+ input dpi_wr_valid,
+ input [DATA_BITS-1:0] dpi_wr_bits_data,
+ input [STRB_BITS-1:0] dpi_wr_bits_strb,
+ output logic dpi_rd_valid,
+ output logic [7:0] dpi_rd_bits_id,
+ output logic [DATA_BITS-1:0] dpi_rd_bits_data,
Review comment:
Updated PR.
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