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The following commit(s) were added to refs/heads/main by this push: new 981bf2f fix types (#34) 981bf2f is described below commit 981bf2f32729b37b2ad302052d6c74c3734a17c9 Author: Luis Vega <vegaluisj...@users.noreply.github.com> AuthorDate: Sun Aug 22 18:37:22 2021 -0700 fix types (#34) --- hardware/chisel/Makefile | 16 ++++++++-------- hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala | 2 +- hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala | 2 +- hardware/chisel/src/main/scala/dpi/VTASimDPI.scala | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hardware/chisel/Makefile b/hardware/chisel/Makefile index 0274c17..bbff447 100644 --- a/hardware/chisel/Makefile +++ b/hardware/chisel/Makefile @@ -63,7 +63,7 @@ SANITIZE = 0 CXX_MAJOR := $(shell $(CXX) -dumpversion | sed 's/\..*//') CXX_HAS_ALIGN_NEW := $(shell [ $(CXX_MAJOR) -ge 7 ] && echo true) -config_test = $(TOP_TEST)$(CONFIG) +CONFIG_TEST = $(TOP_TEST)$(CONFIG) ifndef TVM_PATH @@ -182,16 +182,16 @@ $(lib_path): $(verilator_build_dir)/V$(TOP_TEST).cpp $(cxx_objs) $(CXX) $(ld_flags) $(cxx_flags) $(cxx_objs) $(patsubst %.cpp,%.cpp.o,$(shell find $(verilator_build_dir)/*.cpp)) -o $@ verilator: $(verilator_build_dir)/V$(TOP_TEST).cpp -$(verilator_build_dir)/V$(TOP_TEST).cpp: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v +$(verilator_build_dir)/V$(TOP_TEST).cpp: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv verilator $(verilator_opt) $< -verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).v -$(chisel_build_dir)/$(TOP).$(CONFIG).v: - sbt 'runMain vta.$(CONFIG) --target-dir $(chisel_build_dir) --top-name $(TOP).$(CONFIG)' +verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).sv +$(chisel_build_dir)/$(TOP).$(CONFIG).sv: + sbt 'runMain vta.$(CONFIG) --target-dir $(chisel_build_dir) -o $(TOP).$(CONFIG)' -verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v -$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v: - sbt 'runMain vta.$(config_test) --target-dir $(chisel_build_dir) --top-name $(TOP_TEST).$(CONFIG)' +verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv +$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).sv: + sbt 'runMain vta.$(CONFIG_TEST) --target-dir $(chisel_build_dir) -o $(TOP_TEST).$(CONFIG)' unittest: sbt 'test:runMain unittest.Launcher $(UNITTEST_NAME)' diff --git a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala index 73ae935..5c7c5ee 100644 --- a/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala +++ b/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala @@ -68,7 +68,7 @@ class VTAHostDPIClient extends Bundle with VTAHostDPIParams { class VTAHostDPI extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) - val reset = Input(Bool()) + val reset = Input(Reset()) val dpi = new VTAHostDPIMaster }) addResource("/verilog/VTAHostDPI.v") diff --git a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala index c77bafd..c52260d 100644 --- a/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala +++ b/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala @@ -69,7 +69,7 @@ class VTAMemDPIClient extends Bundle with VTAMemDPIParams { class VTAMemDPI extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) - val reset = Input(Bool()) + val reset = Input(Reset()) val dpi = new VTAMemDPIClient }) addResource("/verilog/VTAMemDPI.v") diff --git a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala index 96654d2..c2e7b6b 100644 --- a/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala +++ b/hardware/chisel/src/main/scala/dpi/VTASimDPI.scala @@ -32,7 +32,7 @@ import vta.shell._ class VTASimDPI extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) - val reset = Input(Bool()) + val reset = Input(Reset()) val dpi_wait = Output(Bool()) }) addResource("/verilog/VTASimDPI.v")