masahi commented on a change in pull request #10839:
URL: https://github.com/apache/tvm/pull/10839#discussion_r839161718
##########
File path: python/tvm/topi/arm_cpu/tensor_intrin.py
##########
@@ -614,21 +614,22 @@ def _instr(index):
ib.emit(outs[0].vstore(0, tvm.tir.const(0, int_32xl)))
return ib.get()
- def pairwise_add_mul(idx):
- # this broadcasts data to the vector size
- a_int8 = ins[0].vload([0], "int8x4")
- re_int32 = tvm.tir.call_intrin("int32", "tir.reinterpret",
a_int8)
- vec_ai32 = re_int32.astype("int32x2")
- vec_a = tvm.tir.call_intrin(int_8xl, "tir.reinterpret",
vec_ai32)
+ # this broadcasts data to the vector size
+ a_int8 = ins[0].vload([0], "int8x4")
+ re_int32 = tvm.tir.call_intrin("int32", "tir.reinterpret", a_int8)
+ vec_ai32 = re_int32.astype("int32x2")
+ vec_a = tvm.tir.call_intrin(int_8xl, "tir.reinterpret", vec_ai32)
- vec_b = ins[1].vload([idx * 2, 0], int_8xl) # we take two
inputs at a time
+ vec_b = ins[1].vload([0, 0], "int8x16")
+ def pairwise_add_mul(extract_half):
+ vec_b_half = tvm.tir.call_intrin("int8x8", extract_half, vec_b)
Review comment:
I made this change while poking around this intrinsic until I get the
correct outputs. But later I realized that the entire diff in this file is
unnecessary, as long as `n_elems = 4` in alter layout. I don't know what
thinking went into the decision of setting `n_elems = 8` before, but the
original intrin code seems to work with `n_elems = 4`.
I'm still keeping my change here since I think loading a 128 bit vector once
and extracting low ad high half is clearer and hopefully faster than doing 64
bit load twice. But I'm happy to revert this change if desired @tkonolige
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscr...@tvm.apache.org
For queries about this service, please contact Infrastructure at:
us...@infra.apache.org
