guberti commented on code in PR #12448:
URL: https://github.com/apache/tvm/pull/12448#discussion_r961859675
##########
python/tvm/relay/op/strategy/arm_cpu.py:
##########
@@ -235,6 +235,28 @@ def conv2d_strategy_arm_cpu(attrs, inputs, out_type,
target):
wrap_topi_schedule(topi.arm_cpu.schedule_depthwise_conv2d_nhwc),
name="depthwise_conv2d_nhwc.arm_cpu",
)
+
+ # Optimized special case depthwiseConv2D operation. Requires a 3x3
kernel, a
+ # NHWC layout, a HWOI kernel layout (which we would ideally
rearrange), no dilation,
+ # "SAME" padding, int8 inputs and outputs, the same number of
input and output
Review Comment:
Fixed! The schedule supports any form of padding - SAME, VALID, or a custom
tuple.
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