LeiWang1999 opened a new pull request, #15106:
URL: https://github.com/apache/tvm/pull/15106
This Pull Request adds support for AMD Matrix Core in TVM.
## Changes Made
The following changes have been made to enable AMD Matrix Core support in
TVM:
- Added ROCm tensor intrins for AMD Matrix Core architecture.
- Added test case of a 1024x1024x1024 dense gemm on each of these
computations
- Implemented the required tile sizes for Matrix FMA (MFMA) computations.
The available tile sizes for MFMA are as follows:
- Integer computation: i8xi8
- Half-precision computation: f16xf16
- Single-precision computation: f32xf32
refer to AMD matrix core
[readme](https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-matrix-cores-readme/),
available tile for the given computations could be:
<html>
<body>
<!--StartFragment-->
A/B Data Format | C/D Data Format | M | N | K | Blocks | Cycles |
Flops/cycle/CU
-- | -- | -- | -- | -- | -- | -- | --
FP32 | FP32 | 32 | 32 | 2 | 1 | 64 | 256
FP32 | FP32 | 16 | 16 | 4 | 1 | 32 | 256
FP16 | FP32 | 32 | 32 | 8 | 1 | 64 | 1024
FP16 | FP32 | 16 | 16 | 16 | 1 | 32 | 1024
INT8 | INT32 | 32 | 32 | 8 | 1 | 64 | 1024
INT8 | INT32 | 16 | 16 | 16 | 1 | 32 | 1024
<!--EndFragment-->
</body>
</html>
For each of these computations, only one intrinsic has been chosen for
implementation. This decision is based on their identical TFLOPS performance.
Considering real-world systems requirements, we have selected a small 'm' tile
and a large 'k' tile to optimize the performance.
Please review the changes and provide any feedback or suggestions for
improvement, see more discussions
[here](https://discuss.tvm.apache.org/t/discussion-support-for-amd-matrix-core/15121).
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