echuraev commented on code in PR #15419:
URL: https://github.com/apache/tvm/pull/15419#discussion_r1282901419
##########
src/runtime/vm/bytecode.cc:
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@@ -338,14 +340,22 @@ Instruction Instruction::AllocTensorReg(RegName storage,
RegName offset, RegName
}
Instruction Instruction::AllocStorage(RegName size, Index alignment,
DLDataType dtype_hint,
- Index device_index, RegName dst) {
+ Index device_index, const
std::vector<int64_t>& shape,
+ RegName dst) {
Instruction instr;
instr.op = Opcode::AllocStorage;
instr.dst = dst;
instr.alloc_storage.allocation_size = size;
instr.alloc_storage.alignment = alignment;
instr.alloc_storage.dtype_hint = dtype_hint;
instr.alloc_storage.device_index = device_index;
+ instr.alloc_storage.ndim = static_cast<uint32_t>(shape.size());
+ if (instr.alloc_storage.ndim > 0) {
+ instr.alloc_storage.shape = new int64_t[shape.size()];
Review Comment:
Thank you. Fixed.
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