[Sorry for the almost-fullquote.] On 18.01.2008 19:24, ron minnich wrote: > With the as-yet uncommitted patch I just posted, we're getting much > better results. My comments in [[[]]] > > LinuxBIOS-3.0.0 Fri Jan 18 08:34:27 PST 2008 starting... > Choosing fallback boot. > LAR: Attempting to open 'fallback/initram/segment0'. > LAR: Start 0xfff80000 len 0x80000 > LAR: seen member normal/payload/segment0 > LAR: seen member normal/payload/segment1 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > LAR: Run file fallback/initram/segment0 failed: No such file. > Fallback failed. Try normal boot > LAR: Attempting to open 'normal/initram/segment0'. > LAR: Start 0xfff80000 len 0x80000 > LAR: seen member normal/payload/segment0 > LAR: seen member normal/payload/segment1 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/initram/segment0 > LAR: CHECK normal/initram/segment0 @ 0xfff9ae20 > start 0xfff9ae70 len 5400 reallen 5400 compression 0 entry 0x00000f0b > loadaddress 0x00000000 > Entry point is 0xfff9bd7b > Hi there from stage1 > done preinit > done gpio init > pll_reset: read msr 0x4c000014 > _MSR GLCP_SYS_RSTPLL (4c000014) value is: 0000059c:0000182e > Configuring PLL > Resetting the processor after PLL configuration for the changes to take effect > > > [[[Note the new message ... So we're through pll reset as before. ]]] >
Yes. And the message makes it clear why we reset the processor. > LinuxBIOS-3.0.0 Fri Jan 18 08:34:27 PST 2008 starting... > Choosing fallback boot. > LAR: Attempting to open 'fallback/initram/segment0'. > LAR: Start 0xfff80000 len 0x80000 > LAR: seen member normal/payload/segment0 > LAR: seen member normal/payload/segment1 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/initram/segment0 > LAR: seen member bootblock > LAR: File not found! > LAR: Run file fallback/initram/segment0 failed: No such file. > Fallback failed. Try normal boot > LAR: Attempting to open 'normal/initram/segment0'. > LAR: Start 0xfff80000 len 0x80000 > LAR: seen member normal/payload/segment0 > LAR: seen member normal/payload/segment1 > LAR: seen member normal/option_table > LAR: seen member normal/stage2/segment0 > LAR: seen member normal/stage2/segment1 > LAR: seen member normal/initram/segment0 > LAR: CHECK normal/initram/segment0 @ 0xfff9ae20 > start 0xfff9ae70 len 5400 reallen 5400 compression 0 entry 0x00000f0b > loadaddress 0x00000000 > Entry point is 0xfff9bd7b > Hi there from stage1 > done preinit > done gpio init > pll_reset: read msr 0x4c000014 > _MSR GLCP_SYS_RSTPLL (4c000014) value is: 0000059c:07de002e > Done pll_reset > done pll reset > [[[I'm skipping the DRAM spew .. nothing new]]] > [[I'm skipping the LAR walk to stage 2..]]] > dev_id_string: Unknown device ID type: 0 > find_constructor: find Unknown > [[[ Wha'ts this mean? It means the id is not set in the dts. This will > be fixed over time ]]] > [[[ But it does not always matter. In the dev_init, I should skip > devices of type Unkown anyway.]]] > find_constructor: check all_constructors[i] 0x0000a400 > find_constructor: cons 0x0000a400, cons id PCI_DOMAIN: 1022:2080 > find_constructor: cons 0x0000a414, cons id APIC_CLUSTER: 1022:2080 > find_constructor: cons 0x0000a428, cons id PCI: 1022:2080 > find_constructor: check all_constructors[i] 0x0000a740 > find_constructor: cons 0x0000a740, cons id PCI: 1022:2090 > dev_id_string: Unknown device ID type: 0 > find_constructor: find Unknown > find_constructor: check all_constructors[i] 0x0000a400 > find_constructor: cons 0x0000a400, cons id PCI_DOMAIN: 1022:2080 > find_constructor: cons 0x0000a414, cons id APIC_CLUSTER: 1022:2080 > find_constructor: cons 0x0000a428, cons id PCI: 1022:2080 > find_constructor: check all_constructors[i] 0x0000a740 > find_constructor: cons 0x0000a740, cons id PCI: 1022:2090 > dev_id_string: Unknown device ID type: 0 > find_constructor: find Unknown > find_constructor: check all_constructors[i] 0x0000a400 > find_constructor: cons 0x0000a400, cons id PCI_DOMAIN: 1022:2080 > find_constructor: cons 0x0000a414, cons id APIC_CLUSTER: 1022:2080 > find_constructor: cons 0x0000a428, cons id PCI: 1022:2080 > find_constructor: check all_constructors[i] 0x0000a740 > find_constructor: cons 0x0000a740, cons id PCI: 1022:2090 > dev_id_string: Unknown device ID type: 0 > find_constructor: find Unknown > find_constructor: check all_constructors[i] 0x0000a400 > find_constructor: cons 0x0000a400, cons id PCI_DOMAIN: 1022:2080 > find_constructor: cons 0x0000a414, cons id APIC_CLUSTER: 1022:2080 > find_constructor: cons 0x0000a428, cons id PCI: 1022:2080 > find_constructor: check all_constructors[i] 0x0000a740 > find_constructor: cons 0x0000a740, cons id PCI: 1022:2090 > dev_id_string: Unknown device ID type: 0 > find_constructor: find Unknown > find_constructor: check all_constructors[i] 0x0000a400 > find_constructor: cons 0x0000a400, cons id PCI_DOMAIN: 1022:2080 > find_constructor: cons 0x0000a414, cons id APIC_CLUSTER: 1022:2080 > find_constructor: cons 0x0000a428, cons id PCI: 1022:2080 > find_constructor: check all_constructors[i] 0x0000a740 > find_constructor: cons 0x0000a740, cons id PCI: 1022:2090 > find_constructor: find PCI_DOMAIN: 1022:2080 > find_constructor: check all_constructors[i] 0x0000a400 > find_constructor: cons 0x0000a400, cons id PCI_DOMAIN: 1022:2080 > find_constructor: match > > > [[[OK, that was the dev_init code. The key thing here is the 'match' > -- we found the constructor for the > north bridge and have set the ops for it. As we add pciid properties > to the various dts'es, there will be more > matches. ]]] > > Phase 1: Very early setup... > Phase 1: done > > [[[ here comes the good news ...]]] > > Show all devs... > root(Root Device): enabled 1 have_resources 0 initialized 0 > cpus: Unknown device path type: 0 > cpus(): enabled 1 have_resources 0 initialized 0 > device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0 > southbridge(PCI: 00:0f.1): enabled 1 have_resources 0 initialized 0 > superio: Unknown device path type: 0 > superio(): enabled 0 have_resources 0 initialized 0 > domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0 > Phase 2: Early setup... > dev_phase2: dev root: dev_phase2: ops 0x00007e20 > ops->phase2_setup_scan_bus 0x00000000 > > dev_phase2: dev cpus: dev_phase2: ops 0x00000000 > ops->phase2_setup_scan_bus 0x0000780b > > dev_phase2: dev device0_0: dev_phase2: ops 0x00000000 > ops->phase2_setup_scan_bus 0x0000780b > > dev_phase2: dev southbridge: dev_phase2: ops 0x00000000 > ops->phase2_setup_scan_bus 0x0000780b > > dev_phase2: dev superio: dev_phase2: ops 0x00000000 > ops->phase2_setup_scan_bus 0x0000780b > > dev_phase2: dev domain0: dev_phase2: ops 0x0000a460 > ops->phase2_setup_scan_bus 0x00005b5a > Calling phase2 phase2_setup_scan_bus...>> Entering northbridge.c: > geodelx_pci_domain_phase2 > Enter northbridge_init_early > writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 > writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 > sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 > sizeram: sizem 0x100MB > sysmem_init: enable for 256MBytes > Usable RAM: 268304383 bytes > sysmem_init: MSR 0x10000028, val 0x2000000f:0xfdf00100 > sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 > sizeram: sizem 0x100MB > SMMGL0Init: 268304384 bytes > SMMGL0Init: offset is 0x80400000 > SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 > writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 > writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 > writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 > sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 > sizeram: sizem 0x100MB > sysmem_init: enable for 256MBytes > Usable RAM: 268304383 bytes > sysmem_init: MSR 0x4000002a, val 0x2000000f:0xfdf00100 > SMMGL1Init: > SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 > writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 > writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 > CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 > CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 > L2 cache enabled > GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 > GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 > Exit northbridge_init_early > > [[[ WOO HOO! north bridge setup and memory setup for 256M!]]] > Great! Any patch combination that achieves this has my Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Please go ahead and check in. > [[[ here comes the bad news ]]] > chipsetinit: Could not find the south bridge! > [[[ damn!]]] > Is this same situation as before or is it worse? If it is worse, please try to fix before you commit. Could it be that we try to find the south bridge by PCI ID and the VSA is needed for that? > Before VSA: > After VSA: > Finding PCI configuration type. > PCI: Sanity check failed > pci_check_direct failed > > [[[ So, Marc, now what :-) ]]] > Regards, Carl-Daniel -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
