Thanks for the explanations, however vague ;-). I thought I was the only one wandering in the dark..
On Thu, 2008-01-17 at 23:38 -0800, ron minnich wrote: > other indexes, there is. Does this mean that the superio.c file fails > to > > configure this io port? > > yes, it means that the port is not configured. There is a lot of TODO > in this file. > It may be time to fill it in. > > Might this also be the cause of the NVIDIA X11 driver not working yet? Can you just give me a push in the right direction how to 'fill it in'? How can I configure the SPI io port in LDN 07, index 0x64 and 0x65 and what io address to configure it to? Can I just pick 0x820 like the vendor bios does? Or do I ask it to the pnp functions (I guess)? What pnp function to use? Is there some more complete example superio chip that does similar things to do the copycat monkey-learns-trick? Hope the 1/2 day off was worth it... Ronald. -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
