This patch fixes the decoding of the IO address range 0x0820->0x0827 into the
LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
interface of the IT8716 SIO chip.
Changes :
1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
functions of a PNP device can have more than 12 resources (ex the GPIO function
of IT8716f), in which case one could have an "array overflow" inside the device
structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
device init time..)
2) - define resource masks for the GPIO function in
src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
by the init code
3) - enable the flash SPI interface into
src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
into the GPIO function). I know that this is problematic because not all m57sli
boards are SPI, but .. do anyone have a better idea how to handle this?..
Signed-off-by: Florentin Demetrescu <[EMAIL PROTECTED]>
Patch file attached.
Thanks,
Florentin
PS: By the way, with all due respect, Gentlemen, I think that keeping 2
(potentially incoherent) sets of resource definitions for PNP devices in 2
different places (<mobo>/Config.lb vs. <sio>/superio.c) is trully brain
dammaging.. Juste my 2 (euro-)cents
Index: coreboot-v2_spi_debug_final/src/include/device/device.h
===================================================================
--- coreboot-v2_spi_debug_final/src/include/device/device.h (revision 3086)
+++ coreboot-v2_spi_debug_final/src/include/device/device.h (working copy)
@@ -55,7 +55,7 @@
unsigned disable_relaxed_ordering : 1;
};
-#define MAX_RESOURCES 12
+#define MAX_RESOURCES 24
#define MAX_LINKS 8
/*
* There is one device structure for each slot-number/function-number
Index: coreboot-v2_spi_debug_final/src/superio/ite/it8716f/superio.c
===================================================================
--- coreboot-v2_spi_debug_final/src/superio/ite/it8716f/superio.c (revision 3086)
+++ coreboot-v2_spi_debug_final/src/superio/ite/it8716f/superio.c (working copy)
@@ -152,7 +152,7 @@
{&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
{0x7ff, 0x4},},
{&ops, IT8716F_KBCM, PNP_IRQ0,},
- {&ops, IT8716F_GPIO,},
+ {&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
{&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
{&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
{&ops, IT8716F_IR,},
Index: coreboot-v2_spi_debug_final/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- coreboot-v2_spi_debug_final/src/mainboard/gigabyte/m57sli/Config.lb (revision 3086)
+++ coreboot-v2_spi_debug_final/src/mainboard/gigabyte/m57sli/Config.lb (working copy)
@@ -290,7 +290,7 @@
# Simple I/O base
io 0x62 = 0x800
# Serial Flash I/O (SPI only)
- #io 0x64 = 0x820
+ io 0x64 = 0x820
# watch dog force timeout (parallel flash only)
#irq 0x71 = 0x1
# No WDT interrupt
--
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