Carl-Daniel Hailfinger wrote:
>> +
>> + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID
>> PIN# */
>> + smp_write_intsrc(mc, mp_ExtINT,
>> + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
>> + 0x0, apicid_sb600, 0x0);
>>
>>
>
> Please use a helper macro for the block below. Suggested macro and
> example follows. You may want to perform an automatic search and replace
> for this.
>
> +/* ISA ints are edge-triggered, and usually originate from the ISA bus,
> + * or its remainings.
> + */
> +#define ISA_INT(intr, pin)\
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
> bus_isa, (intr), apicid_sb600,(pin))
> +
> + ISA_INT(0x1, 0x1);
> + ISA_INT(0x0, 0x2);
> + ISA_INT(0x3, 0x3);
> + ISA_INT(0x4, 0x4);
> + ISA_INT(0x6, 0x6);
> + ISA_INT(0x7, 0x7);
> + ISA_INT(0xd, 0xd);
> + ISA_INT(0xe, 0xe);
>
I suggest we rather check-in this code quickly, and you can send a patch
instead of pasting the correction into a mail? How does that sound?
While I fully agree your suggestion is absolutely a good thing, we
should get the code in first and then improve it over time.
Stefan
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
