note to all: we did find, long ago, on one mainboard with one particular chip, that a POST cycle at the wrong time would hang flashrom. The issue is that every POST cycle is a failed cycle, in the sense that no device ever responds. The chipset timeout cycle was long enough to glitch the timing.
Linux does indeed have some POST cycles in the kernel. So, it is possible that on some chipsets, now and in the future, this could be an issue. The best part is that the actual problem can appear or not appear depending on chipset, revision, and bios revision. Isn't that fun? Just an FYI. thanks ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot