Author: eswierk
Date: 2008-10-14 01:18:56 +0200 (Tue, 14 Oct 2008)
New Revision: 3656
Added:
trunk/coreboot-v2/src/mainboard/intel/truxton/
trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb
trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c
trunk/coreboot-v2/src/mainboard/intel/truxton/chip.h
trunk/coreboot-v2/src/mainboard/intel/truxton/irq_tables.c
trunk/coreboot-v2/src/mainboard/intel/truxton/mainboard.c
trunk/coreboot-v2/src/mainboard/intel/truxton/mptable.c
trunk/coreboot-v2/targets/intel/truxton/
trunk/coreboot-v2/targets/intel/truxton/Config.lb
Modified:
trunk/coreboot-v2/src/superio/intel/i3100/i3100.h
Log:
Add support for the Intel EP80579 (Tolapai) Development Kit mainboard
(Truxton).
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Added: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2008-10-13
23:18:56 UTC (rev 3656)
@@ -0,0 +1,187 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 as
+## published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot ROM chip
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of the coreboot bootloader
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET
+ 1)
+
+##
+## Compute where this copy of coreboot will start in the boot ROM
+##
+default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=131072
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+
+makerule ./failover.inc
+ depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c ../romcc"
+ action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c ../romcc"
+ action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i3100
+ device pci_domain 0 on
+ device pci 00.0 on end # IMCH
+ device pci 00.1 on end # IMCH error status
+ device pci 01.0 on end # IMCH EDMA engine
+ device pci 02.0 on end # PCIe port A/A0
+ device pci 03.0 on end # PCIe port A1
+ device pci 04.0 on end # ?
+ device pci 08.0 off end # must be off to boot
+ device pci 0d.0 off end # must be off to boot
+ device pci 0d.1 off end # must be off to boot
+ chip southbridge/intel/i3100
+ # PIRQ line -> legacy IRQ mappings
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+
+ device pci 1d.0 on end # USB (UHCI)
+ device pci 1d.7 on end # USB (EHCI)
+ device pci 1f.0 on # LPC bridge
+ chip superio/intel/i3100
+ device pnp 4e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ device pci 1f.4 on end # ?
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/ep80579
+ device apic 0 on end
+ end
+ end
+end
Added: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2008-10-13
23:18:56 UTC (rev 3656)
@@ -0,0 +1,229 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 as
+## published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_MAX_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses _RAMBASE
+uses CONFIG_GDB_STUB
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CC
+uses HOSTCC
+uses CROSS_COMPILE
+uses OBJCOPY
+
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE = 2 * 1024 * 1024
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Delay timer options
+## Use timer2
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to reset the motherboard from coreboot
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=1
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_LOGICAL_CPUS=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="Truxton"
+default MAINBOARD_VENDOR= "Intel"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
+
+###
+### Coreboot layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+
+###
+### Compute the location and size of where this firmware image
+### (coreboot plus bootloader) will live in the boot rom chip.
+###
+default FALLBACK_SIZE=131072
+
+##
+## coreboot C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD=1
+
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=5
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=5
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end
+
+
Added: trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c 2008-10-13
23:18:56 UTC (rev 3656)
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "pc80/udelay_io.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/intel/i3100/i3100_early_smbus.c"
+#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "northbridge/intel/i3100/raminit_ep80579.h"
+#include "superio/intel/i3100/i3100.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "superio/intel/i3100/i3100_early_serial.c"
+#include "cpu/x86/bist.h"
+#include "spd.h"
+
+#define SIO_GPIO_BASE 0x680
+#define SIO_XBUS_BASE 0x4880
+
+#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 |
DEVPRES_D4F0)
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+static inline int spd_read_byte(u16 device, u8 address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i3100/raminit_ep80579.c"
+#include "sdram/generic_sdram.c"
+#include "../../intel/jarrell/debug.c"
+
+/* #define TRUXTON_DEBUG */
+
+static void main(unsigned long bist)
+{
+ msr_t msr;
+ u16 perf;
+ static const struct mem_controller mch[] = {
+ {
+ .node_id = 0,
+ .f0 = PCI_DEV(0, 0x00, 0),
+ .channel0 = { (0xa<<3)|2, (0xa<<3)|3 },
+ }
+ };
+
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ early_mtrr_init();
+ if (memory_initialized()) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ }
+
+ /* Set up the console */
+ i3100_enable_superio();
+ i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Prevent the TCO timer from rebooting us */
+ i3100_halt_tco_timer();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+#ifdef TRUXTON_DEBUG
+ print_pci_devices();
+#endif
+ enable_smbus();
+ dump_spd_registers();
+
+ sdram_initialize(ARRAY_SIZE(mch), mch);
+ dump_pci_devices();
+ dump_pci_device(PCI_DEV(0, 0x00, 0));
+#ifdef TRUXTON_DEBUG
+ dump_bar14(PCI_DEV(0, 0x00, 0));
+#endif
+
+#ifdef TRUXTON_DEBUG
+ ram_fill(0x00000000, 0x02000000);
+ ram_verify(0x00000000, 0x02000000);
+#endif
+}
Added: trunk/coreboot-v2/src/mainboard/intel/truxton/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/chip.h
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/chip.h 2008-10-13
23:18:56 UTC (rev 3656)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+struct chip_operations mainboard_intel_truxton_ops;
+
+struct mainboard_intel_truxton_config {
+ int nothing;
+};
Added: trunk/coreboot-v2/src/mainboard/intel/truxton/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/irq_tables.c
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/irq_tables.c 2008-10-13
23:18:56 UTC (rev 3656)
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */
+ 0x00, /* u8 Bus 0 */
+ (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
+ 0x0000, /* u16 reserve IRQ for PCI */
+ 0x8086, /* u16 Vendor */
+ 0x5031, /* Device ID */
+ 0x00000000, /* u32 miniport_data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x5e, /* u8 checksum - mod 256 checksum must give zero */
+ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap},
{link, bitmap}, slot, rfu */
+ {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000},
{0x00, 0x0000}}, 0x00, 0x00},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
+
Added: trunk/coreboot-v2/src/mainboard/intel/truxton/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/mainboard.c
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/mainboard.c 2008-10-13
23:18:56 UTC (rev 3656)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_intel_truxton_ops = {
+ CHIP_NAME("Intel Truxton Mainboard")
+};
+
Added: trunk/coreboot-v2/src/mainboard/intel/truxton/mptable.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/mptable.c
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/mptable.c 2008-10-13
23:18:56 UTC (rev 3656)
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "Intel ";
+ static const char productid[12] = "Truxton ";
+ struct mp_config_table *mc;
+ u8 bus_num;
+ u8 bus_isa;
+ u8 bus_pea0 = 0;
+ u8 bus_pea1 = 0;
+ u8 bus_aioc;
+ device_t dev;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+
+ /* AIOC bridge */
+ dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
+ if (dev) {
+ bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 0:04.0\n");
+ bus_aioc = 0;
+ bus_isa = 9;
+ }
+ /* PCIe A0 */
+ dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
+ if (dev) {
+ bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 0:02.0\n");
+ bus_pea0 = 0;
+ }
+ /* PCIe A1 */
+ dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
+ if (dev) {
+ bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 0:03.0\n");
+ bus_pea1 = 0;
+ }
+
+ /* define bus and isa numbers */
+ for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* IOAPIC handling */
+ smp_write_ioapic(mc, 0x8, 0x20, 0xfec00000);
+
+ /* ISA backward compatibility interrupts */
+ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x8, 0x00);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x01, 0x8, 0x01);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x8, 0x02);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x03, 0x8, 0x03);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x04, 0x8, 0x04);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x06, 0x8, 0x06);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x08, 0x8, 0x08);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x09, 0x8, 0x09);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0c, 0x8, 0x0c);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0d, 0x8, 0x0d);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0e, 0x8, 0x0e);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0f, 0x8, 0x0f);
+
+ /* Standard local interrupt assignments */
+ smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x00);
+ smp_write_lintsrc(mc, mp_NMI,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x01);
+
+ /* IMCH/IICH PCI devices */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
+
+ if (bus_pea0) {
+ /* PCIe slot 0 */
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea0, (0<<2)|0, 0x8, 0x10);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea0, (0<<2)|1, 0x8, 0x11);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea0, (0<<2)|2, 0x8, 0x12);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea0, (0<<2)|3, 0x8, 0x13);
+ }
+
+ if (bus_pea1) {
+ /* PCIe slots 1-4 */
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea1, (0<<2)|0, 0x8, 0x10);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea1, (0<<2)|1, 0x8, 0x11);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea1, (0<<2)|2, 0x8, 0x12);
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pea1, (0<<2)|3, 0x8, 0x13);
+ }
+
+ if (bus_aioc) {
+ /* AIOC PCI devices */
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
+ smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
+ }
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
mc->mpe_length);
+
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
+
Modified: trunk/coreboot-v2/src/superio/intel/i3100/i3100.h
===================================================================
--- trunk/coreboot-v2/src/superio/intel/i3100/i3100.h 2008-10-13 21:41:24 UTC
(rev 3655)
+++ trunk/coreboot-v2/src/superio/intel/i3100/i3100.h 2008-10-13 23:18:56 UTC
(rev 3656)
@@ -27,4 +27,6 @@
#define I3100_SP2 0x05 /* Com2 */
#define I3100_WDT 0x06 /* Watchdog timer */
+#define I3100_SUPERIO_CONFIG_PORT 0x4e
+
#endif
Added: trunk/coreboot-v2/targets/intel/truxton/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/intel/truxton/Config.lb
(rev 0)
+++ trunk/coreboot-v2/targets/intel/truxton/Config.lb 2008-10-13 23:18:56 UTC
(rev 3656)
@@ -0,0 +1,40 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 as
+## published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target truxton
+mainboard intel/truxton
+
+## ROM_SIZE is the total number of bytes allocated for coreboot use
+## (normal AND fallback images and payloads).
+option ROM_SIZE = 2 * 1024 * 1024
+
+## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## not including any payload.
+option ROM_IMAGE_SIZE = 128 * 1024
+
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image
+## (including payload) will use
+option FALLBACK_SIZE = ROM_SIZE
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE=1
+ payload /tmp/filo.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "fallback"
--
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