Corey Osgood wrote:
Thanks for your contribution! I know nothing about sb600, so I'll
leave code review to those who know, but for the patch itself, we need
a sign-off before we can commit any patches, see this:
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
Please repost with your sign off, I assume this applies to your other
patch too.
Thanks!
Corey
2008/10/15 Sean Nelson <[EMAIL PROTECTED] <mailto:[EMAIL PROTECTED]>>
sb600 spi driver file for flashrom
Index: sb600spi.c
===================================================================
--- sb600spi.c (revision 0)
+++ sb600spi.c (revision 0)
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2008 Sean Nelson <[EMAIL PROTECTED]
<mailto:[EMAIL PROTECTED]>>
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License as
published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
02110-1301 USA
+ */
+
+/*
+ * SPI interface for SB600
+ */
+
+#include <stdio.h>
+#include <pci/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include "flash.h"
+#include "spi.h"
+
+uint16_t sb600_flashport = 0;
+
+/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
+int fast_spi = 1;
+
+static uint16_t find_sb600_spi_flash_port(uint16_t device_id)
+{
+ struct pci_dev *dev;
+ uint16_t flashport = 0;
+
+ /* sb600's LPC ISA Bridge */
+ dev = pci_dev_find(0x1002, device_id);
+
+ /* SPI Base Address (A0h) */
+ flashport = pci_read_word(dev, 0xa0);
+
+ return flashport;
+}
+
+int sb600_probe_spi_flash(const char *name)
+{
+ sb600_flashport = find_ite_spi_flash_port(0x438d);
+
+ if (sb600_flashport)
+ flashbus = BUS_TYPE_SB600_SPI;
+
+ return (!it8716f_flashport);
+}
+
+int sb600_spi_command(unsigned int writecnt, unsigned int
readcnt, const unsigned char *writearr, unsigned char *readarr)
+{
+ uint8_t busy, speed;
+ int i;
+
+ if (readcnt > 8) {
+ printf("%s called with unsupported readcnt %i.\n",
+ __FUNCTION__, readcnt);
+ return 1;
+ }
+
+ OUTB(writearr[0], sb600_flashport + 0x00);
+ for(i=1; i < (writecnt-1); i++)
+ {
+ OUTB(writearr[i], sb600_flashport + 0x0c);
+ }
+
+ /*
+ * set the SPI clock speed (0x0D)
+ * NormSpeed: bit 5 & 4
+ * FastSpeed: bit 7 & 6
+ *
+ * 33MHz - 01b
+ * 16.5MHz - 11b
+ */
+ speed = (fast_spi ? 1 : 3)<<6;
+ speed = (fast_spi ? 1 : 3)<<4;
+ OUTB(speed, sb600_flashport);
+
+ /*
+ * set the TxByte and RxBytes (0x01)
+ * TxByteCount: bit 3-0
+ * RxByteCount: bit 7-4
+ */
+ OUTB(((writecnt-1)<<4)|(readcnt), sb600_flashport)
+
+ /*
+ * start the command execution (0x02)
+ * ExecuteOpCode: bit 0; start off the SPI command
+ * Reserved: bit 1&2
+ * SpiArbEnable: bit 3; 0 to speed up SPI ROM Access
+ */
+ OUTB((1<<3)|(1<<0), sb600_flashport);
+
+ if (readcnt > 0) {
+ for (i = 0; i < readcnt; i++) {
+ readarr[i] = INB(sb600_flashport + 0x0c);
+ }
+ }
+
+ return 0;
+}
+
+int sb600_spi_chip_read(struct flashchip *flash, uint8_t *buf)
+{
+ int total_size = 1024 * flash->total_size;
+ memcpy(buf, (const char *)flash->virtual_memory, total_size);
+ return 0;
+}
+
+int sb600_spi_chip_write(struct flashchip *flash, uint8_t *buf)
+{
+ int total_size = 1024 * flash->total_size;
+ memcpy((const char*)flash->virtual_memory, buf, total_size);
+ return 0;
+}
+
--
coreboot mailing list: [email protected]
<mailto:[email protected]>
http://www.coreboot.org/mailman/listinfo/coreboot
Thanks to Peter Stuge for help. The SPI interface is for the ATI/AMD
SB600 Southbridge. This was easier than the Fintek SPI interface.
Signed-off-by: Sean Nelson <[EMAIL PROTECTED]>
---
This code was developed using the datasheets and has not been tested.
--
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