> -----Original Message----- > From: Marc Jones [mailto:[EMAIL PROTECTED] > Sent: Thursday, October 16, 2008 10:32 AM > To: Myles Watson > Cc: ron minnich; Tom Sylla; Coreboot > Subject: Re: [coreboot] SimNOW VGA int 1a > > Myles Watson wrote: > > > > > > On Thu, Oct 16, 2008 at 9:49 AM, ron minnich <[EMAIL PROTECTED] > > <mailto:[EMAIL PROTECTED]>> wrote: > > > > On Thu, Oct 16, 2008 at 8:48 AM, Myles Watson <[EMAIL PROTECTED] > > <mailto:[EMAIL PROTECTED]>> wrote: > > >> >> > Check PCI: 1022:2067 > > >> >> > found > > >> >> > 0xb102: return 0x120 > > >> > > >> the wrong # here? > > > > > > Yes. It should be device # 4 as far as I can tell. In the > > debugger when I > > > do a config read to bus 1 dev 4 function 0 I get the right data > > back. When > > > I do a read to bus 1 dev 2 function 0 I get an error that no > device > > > responded. > > > > > > Like I said, I don't know why the reads succeed. > > > > > > > so you need some debug prints in the PCIBIOS support code. > > > > > > Check PCI: 1022:2067 > > PCI: 01:04.0 found > > bus->secondary = 0x1 dev->path.pci.devfn = 0x20 > > 0xb102: return 0x120 > > > > Now I'm confused. I guess 0x120 was correct (the slot is the upper 5 > > bits of the byte), so I'm still looking. Now it makes sense why the > > reads succeed, but the config write failure is puzzling. It's trying > > to write 0xffffffff to the BAR, but that changes the memory map, so > > after that write there's garbage everywhere. I still haven't found > > the config register that gets changed, but it's not in the VGA card's > > space. > > > Which BAR? What is the contents of 0xcf8? Not sure why, but writing > 0xFFFFFFFF to a BAR is to get the size. It shoudl disable the device > before it does that but sometimes they are sloppy and don't.
cf8 = 0x80012010 Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot