Author: hailfinger
Date: 2008-10-16 19:50:08 +0200 (Thu, 16 Oct 2008)
New Revision: 935
Modified:
coreboot-v3/arch/x86/Makefile
coreboot-v3/mainboard/amd/serengeti/Makefile
coreboot-v3/mainboard/gigabyte/m57sli/Makefile
Log:
The option table C file is a generated file and lives inside the build
directory. Look for it there.
Introduce the STAGE0_DYNAMIC_SRC makefile variable to handle this and
other generated stage1 code.
Thanks to Ron for spotting this bug.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile 2008-10-16 16:02:12 UTC (rev 934)
+++ coreboot-v3/arch/x86/Makefile 2008-10-16 17:50:08 UTC (rev 935)
@@ -147,6 +147,7 @@
$(STAGE0_MAINBOARD_SRC) $(STAGE0_CHIPSET_SRC)
STAGE0_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE0_SRC)) \
+ $(patsubst $(obj)/%.c,$(obj)/%.o,$(STAGE0_DYNAMIC_SRC)) \
$(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ))
$(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ)
Modified: coreboot-v3/mainboard/amd/serengeti/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-16 16:02:12 UTC
(rev 934)
+++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-16 17:50:08 UTC
(rev 935)
@@ -22,7 +22,6 @@
STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
- $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
$(src)/arch/x86/stage1_mtrr.c \
$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
$(src)/arch/x86/amd/model_fxx/stage1.c \
@@ -33,6 +32,8 @@
$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
+STAGE0_DYNAMIC_SRC := $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
+
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
$(src)/northbridge/amd/k8/dqs.c \
Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-10-16 16:02:12 UTC
(rev 934)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-10-16 17:50:08 UTC
(rev 935)
@@ -21,7 +21,6 @@
STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
- $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
$(src)/arch/x86/stage1_mtrr.c \
$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
$(src)/arch/x86/amd/model_fxx/stage1.c \
@@ -31,6 +30,8 @@
$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
$(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \
+STAGE0_DYNAMIC_SRC := $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
+
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
$(src)/northbridge/amd/k8/dqs.c \
--
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