On 17.10.2008 18:00, ron minnich wrote:
> On Fri, Oct 17, 2008 at 8:56 AM, Carl-Daniel Hailfinger
> <[EMAIL PROTECTED]> wrote:
>
>
>> By the way, the v3 CAR disable code is almost finished.
>>
>>
>
> That's great news.
>
Totally untested and buggy code follows. I have no way to backup my code
right now, so it goes to the list. Enjoy.
Regards,
Carl-Daniel
Index: corebootv3-via_car/arch/x86/via/stage1.c
===================================================================
--- corebootv3-via_car/arch/x86/via/stage1.c (Revision 0)
+++ corebootv3-via_car/arch/x86/via/stage1.c (Revision 0)
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 cdh
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <mainboard.h>
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <msr.h>
+#include <macros.h>
+#include <cpu.h>
+#include <stage1.h>
+
+#ifdef NO_IDEA_WHETHER_THIS_IS_RELEVANT_ON_C7
+/**
+ * Set the MTRR for initial ram access.
+ * be warned, this will be used by core other than core 0/node 0 or
core0/node0 when cpu_reset.
+ * This warning has some significance I don't yet understand.
+ */
+void set_init_ram_access(void)
+{
+ set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
+}
+#endif
+
+/**
+ * Disable Cache As RAM (CAR) after memory is setup.
+ */
+void disable_car(void)
+{
+ /* Determine new global variable location. Stack organization from top
+ * Top 4 bytes are reserved
+ * Pointer to global variables
+ * Global variables
+ *
+ * Align the result to 8 bytes
+ */
+ const struct global_vars *newlocation = (struct global_vars
*)((RAM_STACK_BASE - sizeof(struct global_vars *) - sizeof(struct global_vars))
& ~0x7);
+ /* Copy global variables to new location. */
+ memcpy(newlocation, global_vars(), sizeof(struct global_vars));
+ /* Set the new global variable pointer. */
+ *(struct global_vars **)(RAM_STACK_BASE - sizeof(struct global_vars *))
= newlocation;
+
+ __asm__ __volatile__(
+ /* We don't need cache as ram for now on */
+ /* disable cache */
+ " movl %cr0, %eax \n"
+ " orl $(0x1<<30),%eax \n"
+ " movl %eax, %cr0 \n"
+
+ /* disable fixed mtrr from now on, it will be enabled by coreboot_ram
again*/
+ " movl $0xC0010010, %ecx \n"
+// " movl $SYSCFG_MSR, %ecx \n"
+ " rdmsr \n"
+ " andl $(~(3<<18)), %eax \n"
+// " andl $(~(SYSCFG_MSR_MtrrFixDramModEn |
SYSCFG_MSR_MtrrFixDramEn)), %eax\n"
+ /* clear sth */
+#warning Must clear MTRR 0x200 and 0x201
+ " wrmsr \n"
+
+ /* Set the default memory type and disable fixed and enable variable
MTRRs */
+ " movl $0x2ff, %ecx \n"
+// " movl $MTRRdefType_MSR, %ecx\n\t"
+ " xorl %edx, %edx \n"
+ /* Enable Variable and Disable Fixed MTRRs */
+ " movl $0x00000800, %eax \n"
+ " wrmsr\n\t"
+
+ /* enable cache */
+ " movl %cr0, %eax \n"
+ " andl $0x9fffffff,%eax \n"
+ " movl %eax, %cr0 \n"
+
+ " wbinvd \n"
+
+ " movl %[newesp], %esp \n"
+ " lcall stage1_phase3 \n"
+ :: [newesp] "i" (newlocation)
+ : "MEMORY");
+}
Index: corebootv3-via_car/arch/x86/amd/k8/stage1.c
===================================================================
--- corebootv3-via_car/arch/x86/amd/k8/stage1.c (Revision 935)
+++ corebootv3-via_car/arch/x86/amd/k8/stage1.c (Arbeitskopie)
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 cdh
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -45,6 +45,7 @@
*/
void disable_car(void)
{
+#warning This is wrong on so many levels. First we kill our cache, then we
back it up? Argh!
/* call the inlined function */
disable_cache_as_ram();
Index: corebootv3-via_car/arch/x86/Makefile
===================================================================
--- corebootv3-via_car/arch/x86/Makefile (Revision 935)
+++ corebootv3-via_car/arch/x86/Makefile (Arbeitskopie)
@@ -125,6 +125,7 @@
else
ifeq ($(CONFIG_CPU_VIA_C7),y)
STAGE0_CAR_OBJ = via/stage0.o
+ STAGE0_ARCH_X86_SRC += via/stage1.c
endif
endif
endif
--
http://www.hailfinger.org/
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