On Sun, Oct 19, 2008 at 3:12 AM, Corey Osgood <[EMAIL PROTECTED]>wrote:
> On Sun, Oct 19, 2008 at 2:47 AM, Carl-Daniel Hailfinger <
> [EMAIL PROTECTED]> wrote:
>
>> Hi Corey,
>>
>> do you happen to have a patch for the board on which you tested RAMinit?
>> It would be cool it you could send it to me/the list even if it is
>> unfinished.
>> Thanks!
>
>
> It's a royal mess, but it's attached. I should have stage2 stuff ready
> tomorrow.
>
> Thanks,
> Corey
>
> and here it is for real this time.
-Corey
Index: mainboard/Kconfig
===================================================================
--- mainboard/Kconfig (revision 933)
+++ mainboard/Kconfig (working copy)
@@ -52,6 +52,11 @@
help
Select this option for various systems from GIGABYTE.
+config VENDOR_JETWAY
+ bool "Jetway"
+ help
+ Select this option for systems from Jetway.
+
config VENDOR_EMULATION
bool "Emulated systems"
help
@@ -70,6 +75,7 @@
source "mainboard/artecgroup/Kconfig"
source "mainboard/emulation/Kconfig"
source "mainboard/gigabyte/Kconfig"
+source "mainboard/jetway/Kconfig"
source "mainboard/pcengines/Kconfig"
choice
Index: mainboard/jetway/Kconfig
===================================================================
--- mainboard/jetway/Kconfig (revision 0)
+++ mainboard/jetway/Kconfig (revision 0)
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Corey Osgood <[EMAIL PROTECTED]>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_JETWAY
+
+config BOARD_JETWAY_J7F2
+ bool "J7F2 Series (INCOMPLETE)"
+ select ARCH_X86
+ select CPU_VIA_C7
+ select OPTION_TABLE
+ select NORTHBRIDGE_VIA_CN700
+ select SOUTHBRIDGE_VIA_VT8237
+ select SUPERIO_FINTEK_F71805F
+ help
+ Jeway J7F2-Series board, may also work for J7F4.
+
+endchoice
+
+config MAINBOARD_DIR
+ string
+ default jetway/j7f2
+ depends BOARD_JETWAY_J7F2
+
Index: mainboard/jetway/j7f2/mainboard.h
===================================================================
--- mainboard/jetway/j7f2/mainboard.h (revision 0)
+++ mainboard/jetway/j7f2/mainboard.h (revision 0)
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define CPU_ADDR_BITS 40
+
Index: mainboard/jetway/j7f2/initram.c
===================================================================
--- mainboard/jetway/j7f2/initram.c (revision 0)
+++ mainboard/jetway/j7f2/initram.c (revision 0)
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define _MAINOBJECT
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <io.h>
+#include <spd.h>
+#include <via_c7.h>
+#include <arch/x86/pci_ops.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <superio/fintek/f71805f/f71805f.h>
+#include <southbridge/via/vt8237/vt8237.h>
+#include <northbridge/via/cn700/cn700.h>
+
+#define SMBUS_IO_BASE 0x0400
+
+u8 spd_read_byte(u16 dev, u8 addr)
+{
+ return smbus_read_byte(dev, addr, SMBUS_IO_BASE);
+}
+
+void find_smbus_devices(u8 min, u8 max)
+{
+ u8 dev;
+ u8 result;
+ for(dev = min; dev < max; dev++)
+ {
+ result = spd_read_byte(dev, SPD_MEMORY_TYPE);
+ switch(result)
+ {
+ case SPD_MEMORY_TYPE_SDRAM: printk(BIOS_DEBUG,
+ "Possible SDRAM spd at address 0x%2x\n", dev);
+ break;
+ case SPD_MEMORY_TYPE_SDRAM_DDR: printk(BIOS_DEBUG,
+ "Possible DDR SDRAM spd at address 0x%2x\n",
dev);
+ break;
+ case SPD_MEMORY_TYPE_SDRAM_DDR2: printk(BIOS_DEBUG,
+ "Possible DDR2 SDRAM spd at address 0x%2x\n",
dev);
+ break;
+ };
+ }
+}
+
+
+void dump_smbus_registers(void)
+{
+ int device;
+ for(device = 1; device < (int)0x80; device++) {
+ int j;
+ //if(spd_read_byte(device, 0) < 0 )
+ // continue;
+ printk(BIOS_DEBUG, "smbus: %02x", device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ u8 byte;
+ status = spd_read_byte(device, j);
+ if (status < 0) {
+ break;
+ }
+ if ((j & 0xf) == 0) {
+ printk(BIOS_DEBUG, "\n%02x: ",j);
+ }
+ byte = status & 0xff;
+ printk(BIOS_DEBUG, "%02x ", byte);
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+}
+
+static void enable_mainboard_devices(void)
+{
+ u32 dev;
+
+ pci_conf1_find_device(0x1106, 0x3227, &dev);
+ /* Disable GP3 */
+ pci_conf1_write_config8(dev, 0x98, 0x00);
+
+ pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata
+ pci_conf1_write_config8(dev, 0x51, 0x1f);
+ pci_conf1_write_config8(dev, 0x58, 0x60);
+ pci_conf1_write_config8(dev, 0x59, 0x80);
+ pci_conf1_write_config8(dev, 0x5b, 0x08);
+
+ pci_conf1_find_device(0x1106, 0x0571, &dev);
+
+ /* Make it respond to IO space */
+ pci_conf1_write_config8(dev, 0x04, 0x07);
+
+ /* Compatibility mode addresses */
+ //pci_conf1_write_config32(dev, 0x10, 0);
+ //pci_conf1_write_config32(dev, 0x14, 0);
+ //pci_conf1_write_config32(dev, 0x18, 0);
+ //pci_conf1_write_config32(dev, 0x1b, 0);
+
+ /* Native mode base address */
+ //pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
+
+ pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3
+ pci_conf1_write_config8(dev, 0x41, 0xf2);
+ pci_conf1_write_config8(dev, 0x42, 0x09);
+ /* I'll be damned if I know what these do */
+ pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e
+ pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00
+}
+
+static void enable_shadow_ram(void)
+{
+ u8 shadowreg;
+
+ printk(BIOS_DEBUG, "Enabling shadow ram\n");
+ /* Enable shadow ram as normal dram */
+ /* 0xc0000-0xcffff */
+ pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
+ /* 0xd0000-0xdffff */
+ pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
+ /* 0xe0000-0xeffff */
+ pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
+
+ /* 0xf0000-0xfffff */
+ shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
+ shadowreg |= 0x30;
+ pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
+
+ /* Do it again for the vlink controller */
+ shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
+ shadowreg |= 0x30;
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
+}
+
+static void enable_vlink(void)
+{
+ printk(BIOS_DEBUG, "Enabling Via V-Link\n");
+
+ /* Enable V-Link statically in 8x mode, using Jetway default values */
+//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
+ //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
+//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
+
+ /* This has to be done last, I think */
+ pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
+}
+
+int main(void)
+{
+ struct board_info ctrl[] = {
+ {
+ .d0f2 = PCI_BDF(0, 0, 2),
+ .d0f3 = PCI_BDF(0, 0, 3),
+ .d0f4 = PCI_BDF(0, 0, 4),
+ .d0f7 = PCI_BDF(0, 0, 7),
+ .d1f0 = PCI_BDF(0, 1, 0),
+ .spd_channel0 = {0x50},
+ },
+ };
+
+ printk(BIOS_DEBUG, "In initram.c main()\n");
+
+ enable_vlink();
+ enable_mainboard_devices();
+ enable_shadow_ram();
+
+ c7_cpu_setup(PCI_BDF(0, 0, 2));
+
+ enable_smbus(SMBUS_IO_BASE);
+ //find_smbus_devices(0x00, 0xff);
+ sdram_set_registers(ctrl);
+ sdram_set_spd_registers(ctrl);
+ ddr2_sdram_enable(ctrl);
+
+ ram_check(0, 640*1024);
+ ram_check((8 * 1024 * 1024), (16 * 1024 * 1024));
+
+ return 0;
+}
Index: mainboard/jetway/j7f2/stage1.c
===================================================================
--- mainboard/jetway/j7f2/stage1.c (revision 0)
+++ mainboard/jetway/j7f2/stage1.c (revision 0)
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <io.h>
+#include <arch/x86/pci_ops.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <superio/fintek/f71805f/f71805f.h>
+#include <northbridge/via/cn700/cn700.h>
+
+/* Placeholders, build fails without them */
+void stop_ap(void)
+{
+ //int noop;
+}
+
+void disable_car(void)
+{
+ //int noop;
+}
+
+
+void hardware_stage1(void)
+{
+ u32 dev;
+
+ post_code(POST_START_OF_MAIN);
+ f71805f_enable_serial(0x2e);
+
+ /* Enable multifunction for northbridge. */
+ pci_conf1_write_config8(0x00, 0x4f, 0x01);
+
+ printk(BIOS_SPEW, "In hardware_stage1()\n");
+ /* Disabled GP3, to keep the system from rebooting automatically */
+ //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC,
&dev);
+ dev = PCI_BDF(0, 17, 0);
+ pci_conf1_write_config8(dev, 0x98, 0x00);
+}
+
+void mainboard_pre_payload(void)
+{
+ //banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}
Index: mainboard/jetway/j7f2/dts
===================================================================
--- mainboard/jetway/j7f2/dts (revision 0)
+++ mainboard/jetway/j7f2/dts (revision 0)
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/{
+ mainboard_vendor = "Jetway";
+ mainboard_name = "J7F2";
+ mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */
+ mainboard_pci_subsystem_device = "0xbeef"; /* TODO */
+ cpus { };
+ [EMAIL PROTECTED] {
+ };
+ [EMAIL PROTECTED] {
+ [EMAIL PROTECTED],0 {
+ };
+ [EMAIL PROTECTED] {
+ /config/("superio/fintek/f71805f/dts");
+ com2enable = "1";
+ };
+ };
+};
Index: mainboard/jetway/j7f2/cmos.layout
===================================================================
--- mainboard/jetway/j7f2/cmos.layout (revision 0)
+++ mainboard/jetway/j7f2/cmos.layout (revision 0)
@@ -0,0 +1,49 @@
+entries
+
+# start-bit length config config-ID name
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+412 4 e 6 debug_level
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+# ID value text
+
+1 0 Disable
+1 1 Enable
+
+2 0 Enable
+2 1 Disable
+
+4 0 Fallback
+4 1 Normal
+
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+
+checksums
+
+checksum 392 1007 1008
+
Index: mainboard/jetway/j7f2/Makefile
===================================================================
--- mainboard/jetway/j7f2/Makefile (revision 0)
+++ mainboard/jetway/j7f2/Makefile (revision 0)
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Corey Osgood <[EMAIL PROTECTED]>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+## TODO
+
+STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
+ ## $(src)/northbridge/via/cn700/initram.c \
+ $(src)/arch/x86/stage1_mtrr.c
+
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+ $(src)/northbridge/via/cn700/initram.c \
+ $(src)/southbridge/via/vt8237/stage1.c \
+ $(src)/lib/ramtest.c \
+ $(src)/arch/x86/pci_ops_conf1.c
+
+STAGE2_MAINBOARD_SRC =
+
+$(obj)/coreboot.vpd:
+ $(Q)printf " BUILD DUMMY VPD\n"
+ $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
+
Index: mainboard/jetway/j7f2/mainboard.c
===================================================================
--- mainboard/jetway/j7f2/mainboard.c (revision 0)
+++ mainboard/jetway/j7f2/mainboard.c (revision 0)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <mainboard.h>
+#include <config.h>
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <cpu.h>
+#include <globalvars.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+
+/* Nothing to do (yet) */
Index: northbridge/via/cn700/cn700.h
===================================================================
--- northbridge/via/cn700/cn700.h (revision 933)
+++ northbridge/via/cn700/cn700.h (working copy)
@@ -18,8 +18,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef NORTHBRIDGE_VIA_CN700_CN700_H
+#define NORTHBRIDGE_VIA_CN700_CN700_H
+
#include <types.h>
-
+
struct board_info {
u32 d0f2, d0f3, d0f4, d0f7, d1f0;
u16 spd_channel0[2];
@@ -59,3 +62,5 @@
#define RAM_COMMAND_PRECHARGE 0x2
#define RAM_COMMAND_MRS 0x3
#define RAM_COMMAND_CBR 0x4
+
+#endif
--
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