Myles Watson wrote:
On Mon, Oct 20, 2008 at 4:10 PM, Marc Jones <[EMAIL PROTECTED]
<mailto:[EMAIL PROTECTED]>> wrote:
Myles Watson wrote:
0 6 0 AMD-8111 PCI
74601022 02300147 06040007 00014000
00000000 00000000 40010100 02001010
FE00FD00 FFE0FFF0 00000000 00000000
00000000 000000C0 00000000 042B00FF
^
ISA isn't set. That might be a problem.
I can't tell that v2 ever sets it. In the 8111 datasheet it looks like
that bit makes it so that bits 8 & 9 of the address get ignored so that
only 256B of every 1024 are accessible. I don't think that's what we want.
Looking for that I found an interesting couple of defines.
include/device/pci_def.h:#define PCI_BRIDGE_CTL_NO_ISA 0x04 /*
Disable bridging of ISA ports */
include/device/pci_def.h:#define PCI_CB_BRIDGE_CTL_ISA 0x04
I can see that they're used in two different places (one for the
hardware, one for the device struct), but it still seems confusing.
You are correct. I misunderstood this setting. I don't think that it
should be set. I think that the problem is probably in the mmio map that
Ron posted yesterday. I'll keep looking at stage2 device init and then
I'll check out what is going on with mmio.
Marc
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Marc Jones
Senior Firmware Engineer
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mailto:[EMAIL PROTECTED]
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