On Wed, Jan 7, 2009 at 10:29 AM, ron minnich <[email protected]> wrote: > On Mon, Jan 5, 2009 at 2:36 PM, Peter Stuge <[email protected]> wrote: >> Myles Watson wrote: >>> This patch adds southbridge/nvidia/ck804 from v2 minimally updated >>> for v3. >> >> Mostly fine, but.. >> >> >>> + /* If that is invalid we will read that from romstrap. */ >>> + if (!eeprom_valid) { >>> + unsigned long mac_pos; >>> + mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ >>> + mac_l = readl(mac_pos) + nic_index; >>> + mac_h = readl(mac_pos + 4); >>> + } >> >> ..this won't work so well in v3 I think. I'd like a LAR file for the >> MAC. > > Yep. Put a #warning here so we can fix it.
Added. > >> >> >>> +#if CONFIG_PCI_ROM_RUN == 1 >>> + pci_dev_init(dev); /* It will init Option ROM. */ >>> +#endif >> >> Should this be in the NIC code? There could be an option ROM for the NIC. >>> +// 0x7a or e3 >>> +#define PREVIOUS_POWER_STATE 0x7A >>> + >>> +#define MAINBOARD_POWER_OFF 0 >>> +#define MAINBOARD_POWER_ON 1 >>> +#define SLOW_CPU_OFF 0 >>> +#define SLOW_CPU__ON 1 >>> + >>> +#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL >>> +#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON >>> +#endif >> >> We should make this a CONFIG_ variable. > > > Actually it should be a cmos option, as in any real mainboard. Code > for this should not be #ifdef'ed. > > A #warning here would be useful too. Added. Rev 1104. Thanks for the reminder. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
