On Sat, Feb 21, 2009 at 2:45 PM, Carl-Daniel Hailfinger > What about scratchpad registers in the CPU which are guaranteed to be > cache-coherent across multiple cores and processors?
Certainly on core 2 with one cpu we can use a scratchpad registers. In the case of core 2 SMP startup, when we get to starting the AP core 1, memory is functional. It is possible that the cpu support code is going to need to provide a locking code framework of some sort, since when and how locks can be done varies quite a bit depending on cpu, chipset, and what part of coreboot we are executing. ron -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
