Author: linux_junkie
Date: 2009-05-02 23:30:57 +0200 (Sat, 02 May 2009)
New Revision: 4251
Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h
trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
Log:
Assign PIRQs in mainboard Config.lb or use the default ones listed in
i82801xx_lpc.c.
Signed-off-by: Joseph Smith <j...@settoplinux.org>
Acked-by: Ronald G. Minnich <rminn...@gmail.com>
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-02
12:42:30 UTC (rev 4250)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-02
21:30:57 UTC (rev 4251)
@@ -31,6 +31,18 @@
#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
struct southbridge_intel_i82801xx_config {
+ /**
+ * Interrupt Routing configuration
+ * If bit7 is 1, the interrupt is disabled.
+ */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
2009-05-02 12:42:30 UTC (rev 4250)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
2009-05-02 21:30:57 UTC (rev 4251)
@@ -36,6 +36,8 @@
#define NMI_OFF 0
+typedef struct southbridge_intel_i82801xx_config config_t;
+
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
@@ -66,7 +68,11 @@
#define PIRQG 0x0A
#define PIRQH 0x0B
-/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your mainboards Config.lb.
+*/
void i82801xx_enable_apic(struct device *dev)
{
@@ -114,18 +120,59 @@
static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
{
- /* Route PIRQA - PIRQD. */
- pci_write_config8(dev, PIRQA_ROUT, PIRQA);
- pci_write_config8(dev, PIRQB_ROUT, PIRQB);
- pci_write_config8(dev, PIRQC_ROUT, PIRQC);
- pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+ if (config->pirqa_routing) {
+ pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+ } else {
+ pci_write_config8(dev, PIRQA_ROUT, PIRQA);
+ }
+
+ if (config->pirqb_routing) {
+ pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+ } else {
+ pci_write_config8(dev, PIRQB_ROUT, PIRQB);
+ }
+
+ if (config->pirqc_routing) {
+ pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+ } else {
+ pci_write_config8(dev, PIRQC_ROUT, PIRQC);
+ }
+
+ if (config->pirqd_routing) {
+ pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+ } else {
+ pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ }
+
/* Route PIRQE - PIRQH (for ICH2-ICH9). */
if (ich_model >= 0x2440) {
- pci_write_config8(dev, PIRQE_ROUT, PIRQE);
- pci_write_config8(dev, PIRQF_ROUT, PIRQF);
- pci_write_config8(dev, PIRQG_ROUT, PIRQG);
- pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+
+ if (config->pirqe_routing) {
+ pci_write_config8(dev, PIRQE_ROUT,
config->pirqe_routing);
+ } else {
+ pci_write_config8(dev, PIRQE_ROUT, PIRQE);
+ }
+
+ if (config->pirqf_routing) {
+ pci_write_config8(dev, PIRQF_ROUT,
config->pirqf_routing);
+ } else {
+ pci_write_config8(dev, PIRQF_ROUT, PIRQF);
+ }
+
+ if (config->pirqg_routing) {
+ pci_write_config8(dev, PIRQG_ROUT,
config->pirqg_routing);
+ } else {
+ pci_write_config8(dev, PIRQG_ROUT, PIRQG);
+ }
+
+ if (config->pirqh_routing) {
+ pci_write_config8(dev, PIRQH_ROUT,
config->pirqh_routing);
+ } else {
+ pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+ }
}
}
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