Author: rminnich
Date: 2009-09-16 01:38:27 +0200 (Wed, 16 Sep 2009)
New Revision: 4636

Modified:
   trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
   trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb
   trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
   trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c
   trunk/coreboot-v2/targets/dell/s1850/Config.lb
Log:
This is an otherwise dead platform. I'm just committing the basics that 
let it build. 

Signed-off-by: Ronald G. Minnich <rminn...@gmail.com>
Acked-by: Ronald G. Minnich <rminn...@gmail.com>




Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb        2009-09-15 
20:40:31 UTC (rev 4635)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb        2009-09-15 
23:38:27 UTC (rev 4636)
@@ -138,8 +138,8 @@
                        device pci 1f.2 on end
                        device pci 1f.3 on end
 
-                       register "pirq_a_d" = "0x8a07030b"
-                       register "pirq_e_h" = "0x85808080"
+                       register "pirq_a_d" = "0x8e8b8f80"
+                       register "pirq_e_h" = "0x80808080"
                end
                device pci 00.0 on end 
                device pci 00.1 on end

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb       2009-09-15 
20:40:31 UTC (rev 4635)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb       2009-09-15 
23:38:27 UTC (rev 4636)
@@ -84,7 +84,7 @@
 ## Build code to export a programmable irq routing table
 ##
 default CONFIG_HAVE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=16
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c   2009-09-15 20:40:31 UTC 
(rev 4635)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c   2009-09-15 23:38:27 UTC 
(rev 4636)
@@ -123,13 +123,13 @@
 #if 0
        display_cpuid_update_microcode();
 #endif
-#if 0
+#if 1
        print_pci_devices();
 #endif
 #if 1
        enable_smbus();
 #endif
-#if 0
+#if 1
 //     dump_spd_registers(&cpu[0]);
        int i;
        for(i = 0; i < 1; i++) {
@@ -141,15 +141,15 @@
        mainboard_set_e7520_leds();     
 //     memreset_setup();
        sdram_initialize(ARRAY_SIZE(mch), mch);
-#if 0
+#if 1
        dump_pci_devices();
 #endif
-#if 0
+#if 1
        dump_pci_device(PCI_DEV(0, 0x00, 0));
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
 
-#if 0 // temporarily disabled 
+#if 1 // temporarily disabled 
        /* Check the first 1M */
 //     ram_check(0x00000000, 0x000100000);
 //     ram_check(0x00000000, 0x000a0000);

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c     2009-09-15 
20:40:31 UTC (rev 4635)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c     2009-09-15 
23:38:27 UTC (rev 4636)
@@ -1,48 +1,53 @@
-/* This file was generated by getpir.c, do not modify! 
-   (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS 
sets up
+/*
+ * This file is part of the coreboot project.
  *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron....@gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
 #include <arch/pirq_routing.h>
 
 const struct irq_routing_table intel_irq_routing_table = {
-       PIRQ_SIGNATURE,  /* u32 signature */
-       PIRQ_VERSION,    /* u16 version   */
-       32+16*17,        /* there can be total 17 devices on the bus */
-       0x00,            /* Where the interrupt router lies (bus) */
-       (0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
-       0,               /* IRQs devoted exclusively to PCI usage */
-       0x8086,          /* Vendor */
-       0x24d0,          /* Device */
-       0,               /* Crap (miniport) */
+       PIRQ_SIGNATURE,
+       PIRQ_VERSION,
+       32 + 16 * 9,/* Max. number of devices on the bus */
+       0x00,                   /* Interrupt router bus */
+       (0x11 << 3) | 0x0,      /* Interrupt router device */
+       0xc20,                  /* IRQs devoted exclusively to PCI usage */
+       0x1106,                 /* Vendor */
+       0x596,                  /* Device */
+       0,                      /* Crap (miniport) */
        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-       0xc4,         /*  u8 checksum , this hase to set to some value that 
would give 0 after the sum of all bytes for this structure (including checksum) 
*/
+       0x66,                   /* Checksum */
        {
                /* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, 
bitmap}, {link, bitmap},  slot, rfu */
-               {0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 
0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
-               {0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 
0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
-               {0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 
0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
-               {0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 
0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
-               {0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-               {0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 
0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
-               {0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 
0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
-               {0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 
0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+               {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 
0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
+               {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 
0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
+               {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 
0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
+               {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 
0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0},
+               {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 
0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
+               {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 
0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
+               {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 
0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
+               {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 
0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
+               {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 
0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
        }
 };
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-        return copy_pirq_routing_table(addr);
+       return copy_pirq_routing_table(addr);
 }
-

Modified: trunk/coreboot-v2/targets/dell/s1850/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/dell/s1850/Config.lb      2009-09-15 20:40:31 UTC 
(rev 4635)
+++ trunk/coreboot-v2/targets/dell/s1850/Config.lb      2009-09-15 23:38:27 UTC 
(rev 4636)
@@ -5,13 +5,13 @@
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
 
-romimage "normal"
-       option CONFIG_USE_FALLBACK_IMAGE=0
-       option CONFIG_ROM_IMAGE_SIZE=0x16000
-       option COREBOOT_EXTRA_VERSION=".0Normal"
-#      payload ../../../payloads/filo.elf
-       payload /tmp/filo.elf
-end
+#romimage "normal"
+#      option CONFIG_USE_FALLBACK_IMAGE=0
+#      option CONFIG_ROM_IMAGE_SIZE=0x16000
+#      option COREBOOT_EXTRA_VERSION=".0Normal"
+##     payload ../../../payloads/filo.elf
+#      payload /tmp/filo.elf
+#end
 
 romimage "fallback" 
        option CONFIG_USE_FALLBACK_IMAGE=1
@@ -21,4 +21,5 @@
        payload /tmp/filo.elf
 end
 
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
+#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"


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