[email protected] wrote: > Author: rminnich > Date: 2009-10-08 18:06:09 +0200 (Thu, 08 Oct 2009) > New Revision: 4745 > > Modified: > trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig > trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig > trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig > Log: > Set MMX and SSE where needed. Note that many boards don't even bother > with this as many boards (AMD in particular) use CAR. > > This list determined by a series of greps etc. on mainboards, no humans > were harmed in the making of this list. > > Signed-off-by: Ronald G. Minnich <[email protected]> > > Acked-by: Peter Stuge <[email protected]> >
Isn't MMX or SSE something attached to a given CPU rather than a socket? I see the correctness of our CPU model being compromised here.. > Modified: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig 2009-10-08 > 15:12:31 UTC (rev 4744) > +++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig 2009-10-08 > 16:06:09 UTC (rev 4745) > @@ -21,3 +21,4 @@ > config CPU_INTEL_SOCKET_PGA370 > bool > default n > + select MMX > > Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig 2009-10-08 > 15:12:31 UTC (rev 4744) > +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig 2009-10-08 > 16:06:09 UTC (rev 4745) > @@ -3,3 +3,5 @@ > default n > select CPU_INTEL_MODEL_69X > select CPU_INTEL_MODEL_6DX > + select MMX > + select SSE > > Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig 2009-10-08 > 15:12:31 UTC (rev 4744) > +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig 2009-10-08 > 16:06:09 UTC (rev 4745) > @@ -4,3 +4,5 @@ > select CPU_INTEL_MODEL_F2X > select CPU_INTEL_MODEL_F3X > select CPU_INTEL_MODEL_F4X > + select MMX > + select SSE > > > -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
