See patch
Some fixes.
Atom does not like 36bit MTRRs in CAR setup.
Enable XIP setup again (works with 32bit MTRRs)
Keep code more similar to 6ex code..

Signed-off-by: Patrick Georgi <patrick.geo...@coresystems.de>
Signed-off-by: Stefan Reinauer <ste...@coresystems.de>

Index: src/cpu/intel/model_106cx/cache_as_ram_post.c
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram_post.c       (revision 2551)
+++ src/cpu/intel/model_106cx/cache_as_ram_post.c       (working copy)
@@ -62,7 +62,7 @@
        "wrmsr\n"
        "movl   $MTRRphysMask_MSR(0), %ecx\n"
        "movl   $(~(1024*1024 -1) | (1 << 11)), %eax\n"
-       "movl   $0x0000000f, %edx\n"    // 36bit address space
+       "movl   $0x00000000, %edx\n"
        "wrmsr\n"
        "movb   $0x35, %al\noutb %al, $0x80\n"
 #endif
@@ -99,7 +99,7 @@
        "wrmsr\n"
        "movl   $MTRRphysMask_MSR(0), %ecx\n"
        "movl   $(~(1024*1024 -1) | (1 << 11)), %eax\n"
-       "movl   $0x0000000f, %edx\n"    // 36bit address space
+       "movl   $0x00000000, %edx\n"
        "wrmsr\n"
 
        "movb   $0x39, %al\noutb %al, $0x80\n"
Index: src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram.inc  (revision 2551)
+++ src/cpu/intel/model_106cx/cache_as_ram.inc  (working copy)
@@ -103,7 +103,6 @@
        //movl  $0x23322332, %eax
        xorl    %eax, %eax
        rep     stosl
-#endif
 
        post_code(0x29)
        /* Enable Cache As RAM mode by disabling cache */
@@ -111,29 +110,33 @@
        orl     $(1 << 30), %eax
        movl    %eax, %cr0
 
-#if 0
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-       /* Enable cache for our code in Flash because we do CONFIG_XIP here */
+       /* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
         movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
-        movl    $0x0000000f, %edx
+        movl    $0x00000000, %edx
         movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
         wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
-#endif
 
        post_code(0x2a)
         /* enable cache */
         movl   %cr0, %eax
        andl    $( ~( (1 << 30) | (1 << 29) ) ), %eax
-        movl   %eax, %cr0
+       movl    %eax, %cr0
+#endif
 
        /* Set up stack pointer */
+#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
+       /* leave some space for the struct ehci_debug_info */
+       movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+#else
        movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+#endif
        movl    %eax, %esp
 
        /* Restore the BIST result */
-- 
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