Hello,
This patch has RS690 function int15.
The VGA BIOS is through int15 getting LCD panel's ID.
The panel's ID is selection by switch.
This functions is reference "AMD RS690 ASIC Family BIOS Developer’s
Guide".
Thanks.
Signed-off-by: Libra Li <libra...@technexion.com>
Index: src/include/vbios.h
===================================================================
--- src/include/vbios.h (revision 0)
+++ src/include/vbios.h (revision 0)
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+
+/* AMD Chipset */
+#define AMD_RS690_INT15 0x4E08
+
+typedef struct __rs690_int15_regs__
+{
+ u8 fun00_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID
+ u8 fun05_tv_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard
+}rs690_int15_regs;
+
+typedef struct __rs690_vbios_regs__
+{
+ rs690_int15_regs int15_regs;
+}rs690_vbios_regs;
+
+/* Initialization interrupt function */
+extern void rs690_vbios_fun_init(rs690_vbios_regs *vbios_regs);
+
Index: src/mainboard/technexion/tim5690/cache_as_ram_auto.c
===================================================================
--- src/mainboard/technexion/tim5690/cache_as_ram_auto.c (revision 4977)
+++ src/mainboard/technexion/tim5690/cache_as_ram_auto.c (working copy)
@@ -145,20 +145,6 @@
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- /* Init Super I/O GPIOs. Done early. */
- it8712f_enter_conf();
- outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
- outb(IT8712F_GPIO, SIO_DATA);
- outb(0x62, SIO_INDEX); // set Simple I/O Base Address 0x200
- outb(0x02, SIO_DATA);
- outb(0x63, SIO_INDEX);
- outb(0x00, SIO_DATA);
- it8712f_exit_conf();
-}
-
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -191,7 +177,6 @@
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- mb_gpio_init();
it8712f_kill_watchdog();
uart_init();
console_init();
Index: src/mainboard/technexion/tim5690/mainboard.c
===================================================================
--- src/mainboard/technexion/tim5690/mainboard.c (revision 4977)
+++ src/mainboard/technexion/tim5690/mainboard.c (working copy)
@@ -26,6 +26,8 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <../southbridge/amd/sb600/sb600.h>
+#include <../superio/ite/it8712f/it8712f.h>
+#include <vbios.h>
#include "chip.h"
#include "tn_post_code.h"
@@ -33,6 +35,47 @@
#define ARA_ADDRESS 0x0C /* Alert Response Address */
#define SMBUS_IO_BASE 0x1000
+
+/* Video BIOS Function Extensions Specification
+ */
+//Callback Sub-Function 00h - Get LCD Panel ID
+#define LCD_PANEL_ID_NO 0x00 /* No LCD */
+#define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */
+#define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */
+#define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */
+#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
+#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
+#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
+//Callback Sub-Function 05h – Select Boot-up TV Standard
+#define TV_MODE_00 0x00 /* NTSC */
+#define TV_MODE_01 0x01 /* PAL */
+#define TV_MODE_02 0x02 /* PALM */
+#define TV_MODE_03 0x03 /* PAL60 */
+#define TV_MODE_04 0x04 /* NTSCJ */
+#define TV_MODE_05 0x05 /* PALCN */
+#define TV_MODE_06 0x06 /* PALN */
+#define TV_MODE_09 0x09 /* SCART-RGB */
+#define TV_MODE_NO 0xff /* No TV Support */
+
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA SIO_BASE+1
+
+/* Global configuration registers. */
+#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
+#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
+
+#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
+#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
+
+
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
@@ -54,6 +97,36 @@
uint64_t uma_memory_base, uma_memory_size;
+/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
+ LDN the register belongs to, before you can access the register. */
+static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+ outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+static void it8712f_enter_conf(void)
+{
+ /* Enter the configuration state (MB PnP mode). */
+
+ /* Perform MB PnP setup to put the SIO chip at 0x2e. */
+ /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+ outb(0x87, IT8712F_CONFIGURATION_PORT);
+ outb(0x01, IT8712F_CONFIGURATION_PORT);
+ outb(0x55, IT8712F_CONFIGURATION_PORT);
+ outb(0x55, IT8712F_CONFIGURATION_PORT);
+}
+
+static void it8712f_exit_conf(void)
+{
+ /* Exit the configuration state (MB PnP mode). */
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+}
+
+
/* set thermal config
*/
static void set_thermal_config(void)
@@ -117,6 +190,48 @@
*/
}
+/* Mainboard specific GPIO setup. */
+void mb_gpio_init(u16 *iobase)
+{
+ /* Init Super I/O GPIOs. Done early. */
+ it8712f_enter_conf();
+ outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
+ outb(IT8712F_GPIO, SIO_DATA);
+ outb(0x62, SIO_INDEX); // set Simple I/O Base Address 0x200
+ outb((*iobase >> 8), SIO_DATA);
+ outb(0x63, SIO_INDEX);
+ outb((*iobase & 0xff), SIO_DATA);
+ it8712f_exit_conf();
+}
+
+/* The LCD's panel id seletion. */
+void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
+{
+ switch (num_id) {
+ case 0x1:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01;
+ break;
+ case 0x2:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02;
+ break;
+ case 0x3:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03;
+ break;
+ case 0x4:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04;
+ break;
+ case 0x5:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05;
+ break;
+ case 0x6:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06;
+ break;
+ default:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO;
+ break;
+ }
+}
+
/*************************************************
* enable the dedicated function in tim5690 board.
* This function called early than rs690_enable.
@@ -126,8 +241,21 @@
struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;
+ rs690_vbios_regs vbios_regs;
+ u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
+ u8 port2;
+
printk_info("Mainboard tim5690 Enable. dev=0x%p\n", dev);
+ mb_gpio_init(&gpio_base);
+
+ /* The LCD's panel id seletion by switch. */
+ port2 = inb(gpio_base+1);
+ lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
+ /* No support TV */
+ vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
+ rs690_vbios_fun_init(&vbios_regs);
+
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
Index: util/x86emu/x86_interrupts.c
===================================================================
--- util/x86emu/x86_interrupts.c (revision 4977)
+++ util/x86emu/x86_interrupts.c (working copy)
@@ -32,6 +32,7 @@
#include <console.h>
#include <io.h>
#endif
+#include <vbios.h>
enum {
PCIBIOS_CHECK = 0xb101,
@@ -170,6 +171,16 @@
return retval;
}
+
+static rs690_vbios_regs rs690_vbios_regs_local;
+
+/* Initialization interrupt function */
+void rs690_vbios_fun_init(rs690_vbios_regs *vbios_regs)
+{
+ rs690_vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id;
+ rs690_vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard;
+}
+
int int15_handler(struct eregs *regs)
{
int res = -1;
@@ -179,6 +190,20 @@
* the mainboard or northbridge code.
*/
switch (regs->eax & 0xffff) {
+ case AMD_RS690_INT15: // For AMD RS690.
+ switch (regs->ebx & 0xff) {
+ case 0x00:
+ regs->eax &= ~(0xff);
+ regs->ebx = (regs->ebx & ~(0xff)) | rs690_vbios_regs_local.int15_regs.fun00_panel_id;
+ res = 0;
+ break;
+ case 0x05:
+ regs->eax &= ~(0xff);
+ regs->ebx = (regs->ebx & ~(0xff)) | rs690_vbios_regs_local.int15_regs.fun05_tv_standard;
+ res = 0;
+ break;
+ }
+ break;
case 0x5f19:
break;
case 0x5f18:
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
