On Sat, Dec 12, 2009 at 02:30:01PM +0100, Stefan Reinauer wrote: > On 12/11/09 8:39 PM, ron minnich wrote: > > On Wed, Dec 9, 2009 at 2:57 AM, Andrew Goodbody > > <andrew.goodb...@tadpole.com> wrote: > > > >> Luc Verhaegen wrote: > >> > >>> We have 892 bytes to our disposal in cmos. We can reserve 128 for > >>> board/cmos versioning, and reserve even 256 for the bootloader, and still > >>> have 512bytes left for coreboot options, which is tons when bits are used > >>> properly and when strings are not used. > >>> > >> Most boards I have used have a maximum space of 256 bytes that includes the > >> RTC. Where does the extra come from? > >> > > On much of my hardware, the most I can assume is 128 bytes - > > subtracting many bytes that are weirdly hardware controlled (such as > > date). > > > > Some of our hardware has 256 bytes. > > > > The io ports only support an 8-bit address I thought? > > > > The ports 0x70/0x71 even only support 7 bits... The 8th bit is used for > NMI control. > > Higher CMOS bytes can be accessed by 0x72/0x73, 0x74/0x75.... > > However, if you try to access the upper 128 bytes by setting the topmost > bit in 0x70 it will just look like the upper 128 byte are a mirror of > the lower 128 bytes. > > Stefan
Ah, my bad, i guess 1024 bits is why my synapses brought up that figure. Still, it should still be possible to segment this up nicely, and then we suddenly do have a lot of space for bools, sets and integers. And maybe a string or two to denote the board. Luc Verhaegen -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot