Rudolf Marek wrote:
I think I can help you. It looks to me that bit 7 at offset 0xe1 is not set as
default anymore (otherwise the code never worked?). You would need to set it
early so VGA gets visible in "enable" phase. The patch fixes that.
Thanks, that bit does solve the problem with finding the video device. I
discovered it indepently about the time you sent the e-mail; it's fairly
well hidden in the actual datasheet, but BIOS porting guide for another
VIA chipset I have mentions it. It also appears to be enabled on a
commented-out line in raminit.c of all places; maybe this was commented
out later? The other bits of the register set in the commented-out line
don't seem to make sense.
Sadly, just enabling the vide device hasn't solved the legacy VGA-bios
problem (although I suppose it would allow Linux to use it). Nothing
comes on-screen from coreboot alone, and cb complains about various
unimplemented interrupts. Appears that SeaBios vgahooks are needed to
get the display adapter to initialize at all, and nothing comes
on-screen until SeaBios runs the legacy VGA bios - apparently second
time. Disabling either initialization, nothing comes on screen again. I
don't see any mention of needing SeaBios to get the VGA working on the
Wiki, although Peter Stuge suggested it. This poses a problem though,
since I'd like to have the screen working as early as possible, and I'm
not certain it's a good idea to initialize it twice in any case. I don't
even see why it would work as it does, since coreboot seems to call the
legacy VGA BIOS before it has initialized SeaBios, yet it would seem to
be running the vgahooks from SeaBios at that point already.
Also vga_enable_console() will hang most of the time; cn700 for example
has that call commented out with a remark of "VGA seems to work without
this, but crash & burn with it". Disabling it seems to have no ill
effects, so far.
Also I
disabled the direct access FB because it was hardcoded. I forgotten what is for,
maybe libv will know. It looks like the code sets VGA framebuffer size to 32MB
(this is hardcoded elsewhere check the comments)
On the board I'm testing this, if the Direct Access FB is disabled, it
won't work at all. In fact, it only boots to screen if direct access
framebuffer size is 16M (which the factory BIOS sets it to) and enabled.
Usually it seems to hang right after SeaBios has ran the calibration
loop in timer_setup().
Unfortunately it is hard to tell as the legacy VGA-bios will
occassionally start doing random stuff (hang, print garbage on serial,
report various random interrupts etc.) until the system is power-cycled.
I don't normally do that as it confuses my USB serial-adapter and just
do a PCI reset instead, making it hard to always tell what part is
bugging. On http://www.coreboot.org/The_EPIA-M/MII section "Legacy VGA
BIOS" it mentions something that is relevant to this (Legacy VGA BIOS
enabling hardware interrupts, which it does, but interrut controller not
being initialized). Unfortunately I can't find the patch it talks about,
and it doesn't seem to be in the source tree.
Additionally, commenting out this section causes only garbage to come up
on screen:
printk_debug("VGA random fixup ...\n");
> +
> +
> + // why it does not rely on std resource system?
> +/*
> pci_write_config8(dev, 0x04, 0x07);
> pci_write_config8(dev, 0x0d, 0x20);
> pci_write_config32(dev,0x10,0xd8000008);
> pci_write_config32(dev,0x14,0xdc000000);
> -
> +*/
Please try the attached patch I think it could fix it.
Enabling the display device works. The rest of the patch doesn't work
for me. So IF the Direct Access Framebuffer is set to 16M and enabled,
the VGA resource registers are left hardcoded, vga_enable_console is not
called, the Legacy VGA BIOS is initialized in both coreboot and SeaBios
and the Legacy VGA BIOS doesn't bomb on random interrupt vector or
something else bizarre, the SeaBios version string comes up on screen
but then SeaBios hangs in do_boot, after printing B of "Booting from".
Without VGA BIOS it gets past this point and starts loading the OS.
(Without display I can't tell exactly how successful it is at this, though).
I'm presently in progress of verifying the resource settings for
overlaps and other errors. I'd appreciate any pointers to examples or
discussion of the "std resource system" and in particular how the
resource allocation is supposed to be done in coreboot presently. The
patch http://www.coreboot.org/The_EPIA-M/MII speaks about would also be
helpful. Or any insight into the coreboot/SeaBios legacy VGA BIOS
inter-operation.
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