Author: stepan
Date: 2010-01-16 14:47:07 +0100 (Sat, 16 Jan 2010)
New Revision: 5012

Modified:
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c
Log:
Micro-optimization: movl $0 --> xorl.

Signed-off-by: Stefan Reinauer <ste...@coresystems.de>
Acked-by: Stefan Reinauer <ste...@coresystems.de>



Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc    2010-01-16 13:42:43 UTC 
(rev 5011)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc    2010-01-16 13:47:07 UTC 
(rev 5012)
@@ -71,7 +71,7 @@
        /* Set cache as ram mask */
        movl    $(MTRRphysMask_MSR(0)), %ecx
        movl    $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
-       movl    $0x00000000, %edx
+       xorl    %edx, %edx
        wrmsr
 
        post_code(0x25)
@@ -113,7 +113,7 @@
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
        /* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
-        xorl    %edx, %edx
+       xorl    %edx, %edx
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
@@ -124,7 +124,7 @@
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
-        movl    $0x00000000, %edx
+       xorl    %edx, %edx
         movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
         wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c
===================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c 2010-01-16 13:42:43 UTC 
(rev 5011)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c 2010-01-16 13:47:07 UTC 
(rev 5012)
@@ -60,7 +60,7 @@
        "wrmsr\n"
        "movl   $MTRRphysMask_MSR(0), %ecx\n"
        "movl   $(~(1024*1024 -1) | (1 << 11)), %eax\n"
-       "movl   $0x00000000, %edx\n"
+       "xorl   %edx, %edx\n"
        "wrmsr\n"
        "movb   $0x35, %al\noutb %al, $0x80\n"
 #endif
@@ -97,7 +97,7 @@
        "wrmsr\n"
        "movl   $MTRRphysMask_MSR(0), %ecx\n"
        "movl   $(~(1024*1024 -1) | (1 << 11)), %eax\n"
-       "movl   $0x00000000, %edx\n"
+       "xorl   %edx, %edx\n"
        "wrmsr\n"
 
        "movb   $0x39, %al\noutb %al, $0x80\n"


-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Reply via email to