-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi,
The sil3114 chip has a class code set to something else then IDE by strap resistor. It took me long time to figure out that this chip is otherwise IDE compatible ;) Try attached patch for coreboot which reprograms it back to IDE mode ;) It should start to work - booting from FILO and from Seabios. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvl5s0ACgkQ3J9wPJqZRNU8fwCg0ImG+JeZyuIpAjBB0OQBxu32 OP0AnjzRNyz6DRdLHLnyfAS+wseQn6a3 =Mc1w -----END PGP SIGNATURE-----
Index: src/drivers/Makefile.inc =================================================================== --- src/drivers/Makefile.inc (revision 5511) +++ src/drivers/Makefile.inc (working copy) @@ -1,2 +1,4 @@ subdirs-y += generic/debug subdirs-y += ati/ragexl +#subdirs-y += si/3114 +driver-y += si/3114/si_sata.c Index: src/drivers/si/3114/si_sata.c =================================================================== --- src/drivers/si/3114/si_sata.c (revision 5511) +++ src/drivers/si/3114/si_sata.c (working copy) @@ -21,33 +21,23 @@ { uint16_t word; uint32_t dword; -#if 0 - word = pci_read_config16(dev, 0x4); - word |= ((1 << 2) |(1<<4)); // Command: 3--> 17 - pci_write_config16(dev, 0x4, word); -#endif - /* some driver change class code to 0x104, but not change deviceid without reason*/ - /* restore it so we don't need to unplug AC power to restore it*/ - - word = pci_read_config16(dev, 0x0a); - if(word!=0x0180) { /* enble change device id and class id*/ dword = pci_read_config32(dev,0x40); dword |= (1<<0); pci_write_config32(dev, 0x40, dword); - word = 0x0180; - pci_write_config16(dev, 0x0a, word); + dword = 0x01018f00; + pci_write_config32(dev, 0x08, dword); /* disable change device id and class id*/ dword = pci_read_config32(dev,0x40); dword &= ~(1<<0); pci_write_config32(dev, 0x40, dword); - printk(BIOS_DEBUG, "Class code restored.\n"); + printk(BIOS_DEBUG, "SIL Class code programmed to 2 channels IDE.\n"); - } + }
fix_sil.patch.sig
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