Signed off by: Xavi Drudis Ferran <xdru...@tinet.cat>
diff -r -u src/cpu/amd/model_10xxx/defaults.h
../coreboot-p/src/cpu/amd/model_10xxx/defaults.h
--- src/cpu/amd/model_10xxx/defaults.h 2010-08-19 08:06:11.000000000 +0200
+++ ../coreboot-p/src/cpu/amd/model_10xxx/defaults.h 2010-08-19
08:09:06.000000000 +0200
@@ -290,9 +290,9 @@
[5] DisPciCfgCpuMstAbtRsp = 1,
[1] SyncFloodOnUsPwDataErr = 1 */
- /* errata 346 - Fam10 C2
+ /* errata 346 - Fam10 C2 -- FIXME at 25.6.2010 should apply to BL-C[23]
too but I can't find their constants
* System software should set F3x188[22] to 1b. */
- { 3, 0x188, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL,
+ { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
0x00400000, 0x00400000 },
/* L3 Control Register */
diff -r -u src/northbridge/amd/amdmct/amddefs.h
../coreboot-p/src/northbridge/amd/amdmct/amddefs.h
--- src/northbridge/amd/amdmct/amddefs.h 2010-08-19 08:06:11.000000000
+0200
+++ ../coreboot-p/src/northbridge/amd/amdmct/amddefs.h 2010-08-19
08:09:06.000000000 +0200
@@ -66,6 +66,7 @@
#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
#define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3)
#define AMD_DR_Dx (AMD_HY_D0)
+#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 )
#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
