See patch.
Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org
Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. This CAR implementation hardcodes the Cache-as-RAM base address to: 0xd0000 - CacheSize so the DCACHE_RAM_BASE is never actually used for this implementation and these sockets. Signed-off-by: Uwe Hermann <u...@hermann-uwe.de> Index: src/cpu/intel/socket_PGA370/Kconfig =================================================================== --- src/cpu/intel/socket_PGA370/Kconfig (Revision 5951) +++ src/cpu/intel/socket_PGA370/Kconfig (Arbeitskopie) @@ -30,10 +30,6 @@ bool default n -config DCACHE_RAM_BASE - hex - default 0xc0000 - config DCACHE_RAM_SIZE hex default 0x01000 Index: src/cpu/intel/socket_FC_PGA370/Kconfig =================================================================== --- src/cpu/intel/socket_FC_PGA370/Kconfig (Revision 5951) +++ src/cpu/intel/socket_FC_PGA370/Kconfig (Arbeitskopie) @@ -26,11 +26,6 @@ select CACHE_AS_RAM select TINY_BOOTBLOCK -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - depends on CPU_INTEL_SOCKET_FC_PGA370 - config DCACHE_RAM_SIZE hex default 0x8000 Index: src/cpu/intel/slot_1/Kconfig =================================================================== --- src/cpu/intel/slot_1/Kconfig (Revision 5951) +++ src/cpu/intel/slot_1/Kconfig (Arbeitskopie) @@ -21,11 +21,6 @@ bool select CACHE_AS_RAM -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_1 - config DCACHE_RAM_SIZE hex default 0x01000 Index: src/cpu/intel/slot_2/Kconfig =================================================================== --- src/cpu/intel/slot_2/Kconfig (Revision 5951) +++ src/cpu/intel/slot_2/Kconfig (Arbeitskopie) @@ -20,11 +20,6 @@ config CPU_INTEL_SLOT_2 bool -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_2 - config DCACHE_RAM_SIZE hex default 0x01000
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
