On 29.10.2010 14:15, Tobias Diedrich wrote:
Hmpf, forgot to compiletest this one and missed the unused pdev,
fixed.
This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c
and vt8237r_lpc.c
Signed-off-by: Tobias Diedrich<ranma+coreb...@tdiedrich.de>
---
Index: src/southbridge/via/vt8237r/vt8237_ctrl.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237_ctrl.c.orig 2010-10-29
14:05:23.000000000 +0200
+++ src/southbridge/via/vt8237r/vt8237_ctrl.c 2010-10-29 14:06:09.000000000
+0200
@@ -168,6 +168,69 @@
}
+static void vt8237a_vlink_init(struct device *dev)
+{
+ u8 reg;
+ device_t devfun7;
+
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
+ /* No pairing NB was found. */
+ if (!devfun7)
+ return;
+
+ /*
+ * This init code is valid only for the VT8237A! For different
+ * sounthbridges (e.g. VT8237S, VT8237R (without plus R)
typo :) maybe was just copied? Did you get the values from orig bios? Or just
copied? For what vlink mode it is 8x? I got some VIA recommended values but they
are bit different 0xb5 is 0x88.
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig 2010-10-29
14:05:39.000000000 +0200
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-10-29 14:06:27.000000000
+0200
@@ -319,6 +319,49 @@
printk(BIOS_SPEW, "Leaving %s.\n", __func__);
}
+static void vt8237a_init(struct device *dev)
Aha now I see why you need the own struct.
+{
+ u32 tmp;
+
+ /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
+ tmp = pci_read_config8(dev, 0x4f);
+ tmp |= 0x08;
+ pci_write_config8(dev, 0x4f, tmp);
+
+ /*
+ * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
+ * bit5: usb power control lines as gpio
+ */
+ pci_write_config8(dev, 0xe4, 0x24);
+ /*
+ * Enable APIC wakeup from INTH
+ * Enable SATA LED, disable special CPU Frequency Change -
+ * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+ */
+ pci_write_config8(dev, 0xe5, 0x69);
+
+ /* Reduce further the STPCLK/LDTSTP signal to 5us. */
+ pci_write_config8(dev, 0xec, 0x4);
+
+ /* Host Bus Power Management Control, maybe not needed */
+ pci_write_config8(dev, 0x8c, 0x5);
+
+ /* Enable HPET at VT8237R_HPET_ADDR. */
+ pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+
+ southbridge_init_common(dev);
+
+ /* FIXME: Intel needs more bit set for C2/C3. */
+
+ /*
+ * Allow SLP# signal to assert LDTSTOP_L.
+ * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.
What is fixme fixme pre revA2?
+ */
+ outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+
+ dump_south(dev);
+}
+
static void vt8237s_init(struct device *dev)
{
u32 tmp;
@@ -541,7 +584,7 @@
.read_resources = vt8237r_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = vt8237r_init,
+ .init = vt8237a_init,
.scan_bus = scan_static_bus,
};
Otherwise fine.
Thanks,
Rudolf
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