Hi,
On 29.10.2010 14:14, Tobias Diedrich wrote:
This adds the m2v directory to src/mainboards/asus and adjusts the Kconfig.
Note:
I added pci irq routing setup based on pirq tables:
pci_fixup_irqs() in irq_tables.c
I didn't see any existing functionality that will just take the pirq
information and use that to setup pci interrupts.
For example, in src/southbridge/via/vt8237r/vt8237r_lpc.c there is
some epia specific setup, which may really belong into the
corresponding mainboard directory...
Hmm the legacy PIC routing may not work. In linux it could. I never tested that.
+ /* Write SB IOAPIC. */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ VT8237R_APIC_ID, IO_APIC_ADDR, 0);
+
+ /* Write NB IOAPIC. */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
I never used the VIA system on multicore CPU, dunno what to do if we have in
fact more cpus... The IDs should be shifted then.
+++ src/mainboard/asus/m2v/dsdt.asl 2010-10-29 14:07:37.000000000 +0200
@@ -0,0 +1,967 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker<nick.bark...@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek<r.ma...@assembler.cz>
+ * Copyright (C) 2010 Tobias Diedrich<ranma+coreb...@tdiedrich.de>
Where you have taken parts of it? Some parts feel like AMD 7xx code? Maybe we
miss copyright here?
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
+{
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr>> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
We dont do patching we do apcigen stuff instead into SSDT.
+
+ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
This cannot be hardcoded.
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ /* global variables */
+ Name(APIC, 0) // 0=>8259, 1=>IOAPIC
+ Name(LINX, 0)
+ Name(OSYS, 0x0000)
+
+ /* very generic stuff */
+
+ /* Port 80 POST */
+
+ OperationRegion (POST, SystemIO, 0x80, 1)
+ Field (POST, ByteAcc, Lock, Preserve)
+ {
+ DBG0, 8
+ }
+
+ Method (DEBG, 1, NotSerialized)
+ {
+ Store (Arg0, DBG0)
+ }
+
I dont think you need this. My philosophy for ACPI code is: Put there only what
is needed even no extra bit more.
+ Method (MIN, 2, NotSerialized)
+ {
+ If (LLess (Arg0, Arg1)) {
+ Return (Arg0)
+ }
+ Return (Arg1)
+ }
+
+ /* generic acpi */
+
+ /* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+ Method(_PIC, 1)
+ {
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, APIC)
+ }
+
+ Scope(\_SB)
+ {
+ /* This method is placed on the top level, so we can make sure
it's the
+ * first executed _INI method.
+ */
+ Method(_INI, 0)
+ {
+ /* Determine the Operating System and save the value in
OSYS.
+ * We have to do this in order to be able to work around
+ * certain windows bugs.
+ *
+ * OSYS value | Operating System
+ * -----------+------------------
+ * 2000 | Windows 2000
+ * 2001 | Windows XP(+SP1)
+ * 2002 | Windows XP SP2
+ * 2006 | Windows Vista
+ * ???? | Windows 7
+ */
+
+ /* Let's assume we're running at least Windows 2000 */
+ Store (2000, OSYS)
+
+ If (CondRefOf(_OSI, Local0)) {
+ /* Linux answers _OSI with "True" for a couple
of
+ * Windows version queries. But unlike Windows
it
+ * needs a Video repost, so let's determine
whether
+ * we're running Linux.
+ */
+
+ If (_OSI("Linux")) {
+ Store (1, LINX)
+ }
+
+ If (_OSI("Windows 2001")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2001 SP1")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2001 SP2")) {
+ Store (2002, OSYS)
+ }
+
+ If (_OSI("Windows 2006")) {
+ Store (2006, OSYS)
+ }
+ }
+ }
+ }
+
You dont need this.
+ /* _PR CPU0 is dynamically supplied by SSDT */
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ *
+ * Package contents:
+ * ofs len desc
+ * 0 1 Value for PM1a_CNT.SLP_TYP register to enter this system
state.
+ * 1 1 Value for PM1b_CNT.SLP_TYP register to enter this system
state. To enter any
+ * given state, OSPM must write the PM1a_CNT.SLP_TYP register
before the
+ * PM1b_CNT.SLP_TYP register.
+ * 2 2 Reserved
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ /*
+ * Prepare to sleep
+ *
+ * Arg0 – An Integer containing the value of the sleeping state (1 for
S1, 2 for S2, etc.)
+ * Return Value: None
+ */
+ Method (_PTS, 1, NotSerialized)
+ {
+ // FIXME: Not implemented
+ }
+
+ /*
+ * Transition to state
+ *
+ * Arg0 – An Integer containing the value of the sleeping state (1 for
S1, 2 for S2, etc.)
+ * Return Value: None
+ */
+ Method (_TTS, 1, NotSerialized)
+ {
+ // FIXME: Not implemented
+ }
+
get rif of those please
+ /*
+ * System wake
+ *
+ * Arg0 – An Integer containing the value of the sleeping state (1 for
S1, 2 for S2, etc.)
+ * Return Value: A Package containing two Integers containing status
and the power supply S-state
+ *
+ * Element 0 – An Integer containing a bitfield that represents
conditions that occurred during sleep.
+ * 0x00000000 – Wake was signaled and was successful
+ * 0x00000001 – Wake was signaled but failed due to lack of power
+ * 0x00000002 – Wake was signaled but failed due to thermal condition
+ * Other values – Reserved
+ * Element 1 – An Integer containing the power supply S-state.
+ * If non-zero, this is the effective S-state the power supply that
was actually entered. This value is used
+ * to detect when the targeted S-state was not entered because of
too much current being drawn from the
+ * power supply. For example, this might occur when some active
device’s current consumption pushes
+ * the system’s power requirements over the low power supply mark,
thus preventing the lower power
+ * mode from being entered as desired.
+ */
+ Method (_WAK, 1, NotSerialized)
+ {
+ // FIXME: Not implemented
+ Return ( Package () {0x00, 0x00} ) /* successful, S0 */
+ }
+
same here
+/*
+OSPM will invoke _GTS, _PTS, _TTS, _WAK, and _BFS in the following order:
+ 1. OSPM decides (through a policy scheme) to place the system into a
sleeping state
+ 2. _TTS(Sx) is run, where Sx is the desired sleep state to enter
+ 3. OSPM notifies all native device drivers of the sleep state transition
+ 4. _PTS is run
+ 5. OSPM readies system for the sleep state transition
+ 6. _GTS is run
+ 7. OSPM writes the sleep vector and the system enters the specified Sx
sleep state
+ 8. System Wakes up
+ 9. _BFS is run
+ 10. OSPM readies system for the return from the sleep state transition
+ 11. _WAK is run
+ 12. OSPM notifies all native device drivers of the return from the sleep
state transition
+ 13. _TTS(0) is run to indicate the return to the S0 state
+*/
+
and here
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00180000)
+ Name (_BBN, 0x00)
+
+ Name (APRT, Package() {
+ /* AGP? */
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
+ /* PCIe graphics bridge */
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
+ /* PCIe bridge */
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
+ /* SATA */
+ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
+ /* IDE */
+ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
+ /* USB */
+ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
+ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
+ Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
+ Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
+ /* PCI bridge */
+ Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
+ Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
+ Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
+ Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
+ })
+ Name (PPRT, Package() {
+ /* ?? */
+ Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
+ /* PCIe graphics bridge */
+ Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
+ /* PCIe bridge */
+ Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
+ /* SATA */
+ Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
+ /* USB */
+ Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
+ Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
+ Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
+ Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
+ /* PCI bridge */
+ Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
+ Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
+ Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
+ Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
+ })
+
+ /* PCI Routing Table */
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (APIC)
+ {
+ Return (APRT)
+ }
+ Return (PPRT)
+ }
+
+ Device (K8T0) { Name (_ADR, 0x00000000) }
+ Device (K8T1) { Name (_ADR, 0x00000001) }
+ Device (K8T2) { Name (_ADR, 0x00000002) }
+ Device (K8T3) { Name (_ADR, 0x00000003) }
+ Device (K8T4) { Name (_ADR, 0x00000004) }
+ Device (K8T5) { Name (_ADR, 0x00000005) }
+ Device (K8T7) { Name (_ADR, 0x00000007) }
no need
+
+ Device (PCI1) { Name (_ADR, 0x00010000) }
+
+ Device (PEGG)
+ {
+ Name (_ADR, 0x00020000)
+ Name (APRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
+ Package (0x04) { 0x0000FFFF, 0x01,
0x00, 0x19 },
+ Package (0x04) { 0x0000FFFF, 0x02,
0x00, 0x1A },
+ Package (0x04) { 0x0000FFFF, 0x03,
0x00, 0x1B },
+ })
+ Name (PPRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03,
LNKH, 0x00 },
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (APIC)
+ {
+ Return (APRT)
+ }
+ Return (PPRT)
+ }
+ }
+
+ Device (PEX0)
+ {
+ Name (_ADR, 0x00030000)
+ Name (APRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
+ Package (0x04) { 0x0000FFFF, 0x01,
0x00, 0x1D },
+ Package (0x04) { 0x0000FFFF, 0x02,
0x00, 0x1E },
+ Package (0x04) { 0x0000FFFF, 0x03,
0x00, 0x1F },
+ })
+ Name (PPRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03,
LNKH, 0x00 },
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (APIC)
+ {
+ Return (APRT)
+ }
+ Return (PPRT)
+ }
+ }
+
+ Device (PEX1)
+ {
+ Name (_ADR, 0x00030001)
+ Name (APRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
+ Package (0x04) { 0x0000FFFF, 0x01,
0x00, 0x21 },
+ Package (0x04) { 0x0000FFFF, 0x02,
0x00, 0x22 },
+ Package (0x04) { 0x0000FFFF, 0x03,
0x00, 0x23 },
+ })
+ Name (PPRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03,
LNKH, 0x00 },
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (APIC)
+ {
+ Return (APRT)
+ }
+ Return (PPRT)
+ }
+ }
+
+ Device (PEX2)
+ {
+ Name (_ADR, 0x00030002)
+ Name (APRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
+ Package (0x04) { 0x0000FFFF, 0x01,
0x00, 0x25 },
+ Package (0x04) { 0x0000FFFF, 0x02,
0x00, 0x26 },
+ Package (0x04) { 0x0000FFFF, 0x03,
0x00, 0x27 },
+ })
+ Name (PPRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02,
LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03,
LNKH, 0x00 },
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (APIC)
+ {
+ Return (APRT)
+ }
+ Return (PPRT)
+ }
+ }
+
+ Device (SATA) { Name (_ADR, 0x000f0000) }
+ Device (PATA) { Name (_ADR, 0x000f0001) }
+
+ Device (PCI6)
+ {
+ Name (_ADR, 0x00130000)
+ Name (APRT, Package () {
+ Package (0x04) { 0x0001FFFF, 0x00,
0x00, 0x11 }, /* IRQ17 */
+ })
+ Name (PPRT, Package () {
+ Package (0x04) { 0x0001FFFF, 0x00,
LNKB, 0x00 },
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (APIC)
+ {
+ Return (APRT)
+ }
+ Return (PPRT)
+ }
+ }
+
+ Device (PCI7)
+ {
+ Name (_ADR, 0x00130001)
+ Name (APR8, Package () {
+ /* PCI slot 1 */
+ Package (0x04) { 0x0006FFFF, 0x00,
0x00, 0x10 },
+ Package (0x04) { 0x0006FFFF, 0x01,
0x00, 0x11 },
+ Package (0x04) { 0x0006FFFF, 0x02,
0x00, 0x12 },
+ Package (0x04) { 0x0006FFFF, 0x03,
0x00, 0x13 },
+
+ /* PCI slot 2 */
+ Package (0x04) { 0x0007FFFF, 0x00,
0x00, 0x11 },
+ Package (0x04) { 0x0007FFFF, 0x01,
0x00, 0x12 },
+ Package (0x04) { 0x0007FFFF, 0x02,
0x00, 0x13 },
+ Package (0x04) { 0x0007FFFF, 0x03,
0x00, 0x10 },
+
+ /* PCI slot 3 */
+ Package (0x04) { 0x0008FFFF, 0x00,
0x00, 0x12 },
+ Package (0x04) { 0x0008FFFF, 0x01,
0x00, 0x13 },
+ Package (0x04) { 0x0008FFFF, 0x02,
0x00, 0x10 },
+ Package (0x04) { 0x0008FFFF, 0x03,
0x00, 0x11 },
+
+ /* PCI slot 4 */
+ Package (0x04) { 0x0009FFFF, 0x00,
0x00, 0x13 },
+ Package (0x04) { 0x0009FFFF, 0x01,
0x00, 0x10 },
+ Package (0x04) { 0x0009FFFF, 0x02,
0x00, 0x11 },
+ Package (0x04) { 0x0009FFFF, 0x03,
0x00, 0x12 },
+ })
+ Name (PPR8, Package () {
+ /* PCI slot 1 */
+ Package (0x04) { 0x0006FFFF, 0x00,
LNKA, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x01,
LNKB, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x02,
LNKC, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x03,
LNKD, 0x00 },
+
+ /* PCI slot 2 */
+ Package (0x04) { 0x0007FFFF, 0x00,
LNKB, 0x00 },
+ Package (0x04) { 0x0007FFFF, 0x01,
LNKC, 0x00 },
+ Package (0x04) { 0x0007FFFF, 0x02,
LNKD, 0x00 },
+ Package (0x04) { 0x0007FFFF, 0x03,
LNKA, 0x00 },
+
+ /* PCI slot 3 */
+ Package (0x04) { 0x0008FFFF, 0x00,
LNKC, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x01,
LNKD, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x02,
LNKA, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x03,
LNKB, 0x00 },
+
+ /* PCI slot 4 */
+ Package (0x04) { 0x0009FFFF, 0x00,
LNKD, 0x00 },
+ Package (0x04) { 0x0009FFFF, 0x01,
LNKA, 0x00 },
+ Package (0x04) { 0x0009FFFF, 0x02,
LNKB, 0x00 },
+ Package (0x04) { 0x0009FFFF, 0x03,
LNKC, 0x00 },
+ })
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (APIC)
+ {
+ Return (APR8)
+ }
+ Return (PPR8)
+ }
+ }
+
+ Device (PCIE)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ Memory32Fixed(ReadOnly,
+ 0xE0000000,
Sorry this cannot be hardcoded. I dont think you need this at all.
+ 0x10000000,
+ )
+ })
+ Return (TMP)
+ }
+ }
+
+ Device (SBRG) { /* southbridge */
+ Name (_ADR, 0x00110000)
+ Device (HPET) {
+ Name (_HID, EisaId ("PNP0103"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ Memory32Fixed(ReadOnly,
+ 0xFED00000,
+ 0x00000400,
+ )
+ IRQNoFlags () {0}
+ IRQNoFlags () {8}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 keyboard (seems to be important for
WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060,
0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064,
0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* Parallel port */
+ Device (LPT0)
+ {
+ Name (_HID, EisaId ("PNP0401"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0378,
0x0378, 0x01, 0x08)
+ IO (Decode16, 0x0778,
0x0778, 0x01, 0x08)
+ IRQNoFlags () {7}
+ DMA (Compatibility,
NotBusMaster, Transfer8) {3}
+ })
+ Return (TMP)
+ }
+ }
+ }
+
+ Name(CRES, ResourceTemplate() {
+ WordBusNumber(ResourceProducer, MinFixed,
MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation
Offset
+ 0x0100, // Length
+ ,,
+ )
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed,
PosDecode, EntireRange,
+ 0x0000, /* address
granularity */
+ 0x0000, /* range
minimum */
+ 0x0CF7, /* range
maximum */
+ 0x0000, /* translation
*/
+ 0x0CF8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed,
PosDecode, EntireRange,
+ 0x0000, /* address
granularity */
+ 0x0D00, /* range
minimum */
+ 0xFFFF, /* range
maximum */
+ 0x0000, /* translation
*/
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000,
VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000,
EMM1) /* Assume C0000-E0000 empty */
+ Memory32Fixed(READONLY, 0x000E0000, 0x00020000,
RDBS) /* BIOS ROM area */
+ /* DRAM Memory from 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000,
0x00000000, DMLO) /* 1MB to TopMem */
+ Memory32Fixed(ReadOnly, 0xE0000000, 0x10000000,
MCFG) /* MMCONFIG area */
+ Memory32Fixed(READONLY, 0xF0000000, 0x10000000,
MMIO) /* PCI mapping space */
+
+#if 0
+ /* BIOS space just below 4GB */
+ DWORDMemory(
+ ResourceProducer, PosDecode, MinFixed,
MaxFixed, Cacheable, ReadWrite,
+ 0x00, /* Granularity
*/
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation
*/
+ 0x00000001, /* Max-Min,
RLEN */
+ ,,
+ PCBM
+ )
+
+ /* BIOS space just below 16EB */
+ QWORDMemory(ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, /* Granularity
*/
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation
*/
+ 0x00000001, /* Max-Min,
RLEN */
+ ,,
+ PEBM
+ )
+#endif
+
+ /* DRAM memory from 4GB to TopMem2 */
+ QWORDMemory(ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, /* Granularity
*/
+ 0x00000000, /* Min */
+ 0x00000000, /* Max */
+ 0x00000000, /* Translation
*/
+ 0x00000001, /* Max-Min,
RLEN */
+ ,,
+ DMHI
+ )
+
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ External(TOM1) /* 32bit top of memory from SSDT */
+ External(TOM2) /* 64bit top of memory from SSDT */
Maybe windows will accept only IO resorce without any memory resource. It is
PITA. Please try to investigate what we should relly tell here:
Name(CRES, ResourceTemplate() {
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode,
EntireRange,
0x0000, /* address granularity */
0x0000, /* range minimum */
0x0CF7, /* range maximum */
0x0000, /* translation */
0x0CF8 /* length */
)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode,
EntireRange,
0x0000, /* address granularity */
0x0D00, /* range minimum */
0xFFFF, /* range maximum */
0x0000, /* translation */
0xF300 /* length */
)
}) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) {
/* DBGO("\\_SB\\PCI0\\_CRS\n") */
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
} /* End Device(PCI0) */
If this works for XP it would be nice...
+ Scope (\_SB)
+ {
+ OperationRegion (PCI0.SBRG.PIX0, PCI_Config, 0x55, 0x04)
+ OperationRegion (PCI0.SBRG.PIX1, PCI_Config, 0x50, 0x02)
+ OperationRegion (PCI0.SBRG.PIX2, PCI_Config, 0x44, 0x02)
+ OperationRegion (PCI0.SBRG.PIX3, PCI_Config, 0x67, 0x03)
+ OperationRegion (PCI0.SBRG.PIX4, PCI_Config, 0x6C, 0x04)
+ OperationRegion (PCI0.SBRG.PIEF, PCI_Config, 0x46, 0x01)
This code comes from where? You wrote it?
+ Field (PCI0.SBRG.PIX0, ByteAcc, NoLock, Preserve)
+ {
+ , 4,
+ PIRA, 4,
+ PIRB, 4,
+ PIRC, 4,
+ , 4,
+ PIRD, 4,
+ , 4
+ }
+ Field (PCI0.SBRG.PIX1, ByteAcc, NoLock, Preserve)
+ {
+ , 1,
+ EP3C, 1,
+ EN3C, 1,
+ , 6,
+ KBFG, 1
+ }
+ Field (PCI0.SBRG.PIX2, ByteAcc, NoLock, Preserve)
+ {
+ PIRE, 4,
+ PIRF, 4,
+ PIRG, 4,
+ PIRH, 4,
+ }
+ Field (PCI0.SBRG.PIX3, ByteAcc, NoLock, Preserve)
+ {
+ ENIR, 1,
+ IRSD, 1,
+ Offset (0x02),
+ IRBA, 8
+ }
+ Field (PCI0.SBRG.PIX4, ByteAcc, NoLock, Preserve)
+ {
+ PS0E, 1,
+ PS1E, 1,
+ ROME, 1,
+ APCE, 1,
+ LPMS, 2,
+ MSEN, 1,
+ IXEN, 1,
+ LPMD, 2,
+ MDEN, 1,
+ GMEN, 1,
+ LPLP, 2,
+ LPEN, 1,
+ FDEN, 1,
+ LPCA, 3,
+ CAEN, 1,
+ LPCB, 3,
+ CBEN, 1,
+ LPSB, 2,
+ SBEN, 1,
+ FDSE, 1,
+ Offset (0x04)
This looks suspicius. We cannot copy anything from orig bios. I think you dont
need legacy IRQ anyway windows should work with APIC only. Please try to keep
the ACPI stuff as simple as possible.
+/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
+ LDN the register belongs to, before you can access the register. */
+static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+ outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
I think we have some generic function like pnp_enter_ext_func_mode
etc please check it.
+ /*
+ * it8712f gpio config
+ *
+ * Most importantly this switches pin 91 from
+ * PCIRSTIN# to VIN7.
+ * Note that only PCIRST3# and PCIRST5# are affected
+ * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
+ * direct buffers of #LRESET (low pin count bus reset).
+ * If this is not done All PCIRST are in reset state and the
+ * pcie slots don't initialize.
+ *
+ * pci reset handling:
+ * pin 91: VIN7 (alternate PCIRSTIN#)
+ * pin 48: PCIRST5# / gpio port 5 bit 0
+ * pin 84: PCIRST4# / gpio port 1 bit 0
+ * pin 31: PCIRST1# / gpio port 1 bit 4
+ * pin 33: PCIRST2# / gpio port 1 bit 2
+ * pin 34: PCIRST3# / gpio port 1 bit 1
+ *
+ * PCIRST[0-5]# are connected as follows:
+ * pcirst1# -> pci bus
+ * pcirst2# -> ide bus
+ * pcirst3# -> pcie devices
+ * pcirst4# -> pcie graphics
+ * pcirst5# -> maybe n/c (untested)
nice how did you found out?
Btw we usually have sio setup in romstage.c But maybe it makes more sense here
if it is not critical.
Maybe resets and voltage setup should be really in romstage.c (so it is called
before memory etc is setup).
+
+static void m2v_bus_init(void)
+{
+ u8 tmp;
+
+ pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0, 0), K8T890_MULTIPLE_FN_EN,
0x01);
+ /*
+ * Northbridge pcie bridge 3.3 is not connected to anything, hide it.
+ */
+ tmp = pci_cf8_conf1.read8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0);
+ tmp&= ~0x10; /* hide pcie bridge 0:3.3 */
+ tmp&= ~0x40; /* hide scratch register function 0:0.6 */
+ pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0, tmp);
+ /* Enable southbridge bridges 13.0 and 13.1 */
+ pci_cf8_conf1.write8(NULL, 0, PCI_DEVFN(0x11, 7), 0X4F, 0x43);
Hmm this most likely shoudl be done with the help of devicetree.cb
+ /*
+ * Mark APIC memory as reserved to get closer to ASUS E820 map
+ */
+ lb_add_memory_range(mem, LB_MEM_RESERVED, IO_APIC_ADDR, 0x1000);
+ lb_add_memory_range(mem, LB_MEM_RESERVED, K8T890_APIC_BASE, 0x1000);
Dont think this is neccessary.
+ /*
+ * Mark BIOS ROM space as reserved
+ */
+ lb_add_memory_range(mem, LB_MEM_RESERVED, 0xffc00000, 0x400000);
Dont think this is neccessary.
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M2V")
+ .enable_dev = m2v_enable,
+};
Index: src/mainboard/asus/m2v/mptable.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ src/mainboard/asus/m2v/mptable.c 2010-10-29 14:07:37.000000000 +0200
THis was recently fixed are you using fixed version?
+#define SB_VFSMAF 0
I think for you would work normal way (without this ldstop_sb. I had troubles
with integrated VGA on K8M890.
Otherwise well done! Please try to address the remaining issues.
Thanks,
Rudolf
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