Hello,
please advise on EPIA 800 board hanging after northbridge initialisation. I
checked against chipset datasheet and working AWARD dump - the northbridge
SDRAM configuration registers are correctly set. There are no errors in
memory test, I can induce errors in memory test for example with wrongly
configured paging registers. I have tested with five different memory
modules (single/double sided, differing speeds, latencys).
I did found an old thread (by Al Hooton) with similar problem, that was
resolved with correct CAS latency setting, does not help in this case.
Outcome does not differ with/without payload(s) and the hardware passes all
tests with AWARD I can throw at it.
Is this rom structure reasonable (missing fallback/romstage?):
CBFSPRINT coreboot.rom
coreboot.rom: 256 kB, bootblocksize 65536, romsize 262144, offset 0x0
Alignment: 64 bytes
Name Offset Type Size
fallback/coreboot_ram 0x0 stage 47306
fallback/payload 0xb940 payload 17021
pci1023,8500.rom 0xfc00 optionrom 49152
(empty) 0x1bc40 null 82808
What I get out from console with SPEW:
coreboot-4.0-r6016M Wed Nov 3 21:17:24 EET 2010 starting...
87 is the comm register
SMBus controller enabled
vt8601 init starting
00000000 is the north
1106 0601
0120d4 is the computed timing
NOP
PRECHARGE
DUMMY READS
CBR
MRS
NORMAL
set ref. rate
enable multi-page open
Slot 00 is SDRAM 20000000 bytes
000e is the MA type
Slot 01 is empty
Slot 02 is empty
Slot 03 is empty
vt8601 done
<northbridge dump>
00:06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00
10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50:ac 08 80 00 00 00 40 40 e0 00 40 40 40 40 40 40
60:3f 00 00 31 e6 95 95 00 52 3c 86 0d 08 7f 00 00
70:00 00 00 00 00 00 00 00 01 f0 00 00 00 00 00 00
80:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0:02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00
b0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0:00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00
<memory tests>
Testing DRAM : 00000000-000a0000
DRAM fill: 00000000-000a0000
000a0000
DRAM filled
DRAM verify: 00000000-000a0000
000a0000
DRAM range verified.
Done.
Testing DRAM : 00100000-01000000
DRAM fill: 00100000-01000000
01000000
DRAM filled
DRAM verify: 00100000-01000000
01000000
DRAM range verified.
Done.
Loading stage image.
Check CBFS header at <hangs here>
With lower loglevel:
coreboot-4.0-r6016M Wed Nov 3 21:30:53 EET 2010 starting...
vt8601 init starting
Slot 00 is SDRAM 20000000 bytes
Slot 01 is empty
Slot 02 is empty
Slot 03 is empty
vt8601 done
Stage: loading fallback/coreboot_ram @ 0x <hangs here>
Regards,
Toomas Pruuden
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