Linux also needs the MMCONF area to be reserved either in E820 or
as an ACPI motherboard resource or it will not enable MMCONFIG
and the extended pcie configuration area will be unaccessible:
This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm not sure if the choice for the index parameter of new_resource()
is correct though.
Note that the bios rom decode is enabled in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
for the whole 4MB area (even though the comment says 1MB).
dmesg excerpt without patch:
|BIOS-provided physical RAM map:
| BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
| BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
| BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
| BIOS-e820: 0000000000100000 - 00000000dffed000 (usable)
| BIOS-e820: 00000000dffed000 - 00000000e0000000 (reserved)
| BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
[...]
|ACPI: bus type pci registered
|PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base
0xe0000000)
|PCI: not using MMCONFIG
|PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=7
|PCI: Using configuration type 1 for base access
|bio: create slab <bio-0> at 0
|ACPI: EC: Look up EC in DSDT
|ACPI: Interpreter enabled
|ACPI: (supports S0 S5)
|ACPI: Using IOAPIC for interrupt routing
|PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base
0xe0000000)
|[Firmware Bug]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in
ACPI motherboard resources
|PCI: not using MMCONFIG
|PCI: DMI: pci_use_crs=1 pci_probe=0000000b
|PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and
report a bug
|ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
|pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7]
|pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff]
|pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff]
dmesg excerpt with patch:
|BIOS-provided physical RAM map:
| BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
| BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
| BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
| BIOS-e820: 0000000000100000 - 00000000dffed000 (usable)
| BIOS-e820: 00000000dffed000 - 00000000f0000000 (reserved)
| BIOS-e820: 00000000fec00000 - 00000000fec00100 (reserved)
| BIOS-e820: 00000000fecc0000 - 00000000fecc0100 (reserved)
| BIOS-e820: 00000000ffc00000 - 0000000100000000 (reserved)
| BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
[...]
|ACPI: bus type pci registered
|PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base
0xe0000000)
|PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
|PCI: Using MMCONFIG for extended config space
|PCI: Using configuration type 1 for base access
|bio: create slab <bio-0> at 0
|ACPI: EC: Look up EC in DSDT
|ACPI: Interpreter enabled
|ACPI: (supports S0 S5)
|ACPI: Using IOAPIC for interrupt routing
|PCI: DMI: pci_use_crs=1 pci_probe=00000008
|PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and
report a bug
|ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
|pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7]
|pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff]
|pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff]
Signed-off-by: Tobias Diedrich <ranma+coreb...@tdiedrich.de>
---
Index: src/southbridge/via/k8t890/k8t890_traf_ctrl.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_traf_ctrl.c.orig 2010-11-10
14:29:57.000000000 +0100
+++ src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2010-11-10
14:30:44.000000000 +0100
@@ -58,7 +58,7 @@
res->limit = res->base + res->size - 1;
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Add an MMCONFIG resource. */
@@ -67,7 +67,7 @@
res->align = log2(res->size);
res->gran = log2(res->size);
res->limit = 0xffffffff; /* 4G */
- res->flags = IORESOURCE_MEM;
+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
}
static void traf_ctrl_enable_generic(struct device *dev)
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig 2010-11-10
14:29:57.000000000 +0100
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-11-10 14:53:16.000000000
+0100
@@ -521,7 +521,7 @@
res->base = VT8237R_ACPI_IO_BASE;
res->size = 128;
res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Fixed EISA ECLR I/O Regs */
@@ -529,7 +529,7 @@
res->base = 0x4d0;
res->size = 2;
res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Fixed System Management Bus I/O Resource */
@@ -537,7 +537,7 @@
res->base = VT8237R_SMBUS_IO_BASE;
res->size = 16;
res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Fixed APIC resource */
@@ -547,7 +547,15 @@
res->limit = 0xffffffffUL;
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Fixed flashrom resource */
+ res = new_resource(dev, 4);
+ res->base = 0xff800000UL;
+ res->size = 0x00800000UL; /* 8MB */
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
res = new_resource(dev, 1);
--
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