Rudolf Marek wrote:
> +/*
> + Following table comes directly from BKDG (unbuffered DIMM support)
> + [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1=present 0=empty
> + X uses same layout but 1 means double rank 0 is single rank/empty
> +*/
> +
Maybe clarify that ch{0_0,1_0,0_1,1_1} maps to MEMCS_{1L,1H,2L,2H} in
the PDF. Maybe also mention that preE is table 45, and revE table 46.
> + static const unsigned char dimm_loading_config_preE[16][16] = {
> + [0x8] = {[0x0] = DDR400,[0x8] = DDR400},
> + [0x2] = {[0x0] = DDR333,[0x2] = DDR400},
> + [0xa] = {[0x0] = DDR400_2T,[0x2] = DDR400_2T,
> + [0x8] = DDR400_2T,[0xa] = DDR333_2T},
> + [0xc] = {[0x0] = DDR400,[0xc] = DDR400},
> + [0x3] = {[0x0] = DDR333,[0x3] = DDR400},
> + [0xf] = {[0x0] = DDR400_2T,[0x3] = DDR400_2T,
> + [0xc] = DDR400_2T,[0xf] = DDR333_2T},
> + };
This matches the PDF.
> + static const unsigned char dimm_loading_config_revE[16][16] = {
> + [0x8] = {[0x0] = DDR400, [0x8] = DDR400},
> + [0x2] = {[0x0] = DDR333, [0x2] = DDR400},
> + [0x4] = {[0x0] = DDR400, [0x4] = DDR400},
> + [0x1] = {[0x0] = DDR333, [0x1] = DDR400},
> + [0xa] = {[0x0] = DDR400_2T, [0x2] = DDR400_2T,
> + [0x8] = DDR400_2T, [0xa] = DDR333_2T},
> + [0x5] = {[0x0] = DDR400_2T, [0x1] = DDR400_2T,
> + [0x4] = DDR400_2T, [0x5] = DDR333_2T},
> + [0xc] = {[0x0] = DDR400, [0xc] = DDR400, [0x4] = DDR400, [0x8]
> = DDR400},
> + [0x3] = {[0x0] = DDR333, [0x1] = DDR333, [0x2] = DDR333, [0x3]
> = DDR400},
> + [0xe] = {[0x0] = DDR400_2T, [0x4] = DDR400_2T, [0x2] =
> DDR400_2T,
> + [0x6] = DDR400_2T, [0x8] = DDR400_2T, [0xc] =
> DDR400_2T,
> + [0xa] = DDR333_2T, [0xe] = DDR333_2T},
> + [0xb] = {[0x0] = DDR333, [0x1] = DDR400_2T, [0x2] = DDR333_2T,
> + [0x3] = DDR400_2T, [0x8] = DDR333_2T, [0x9] =
> DDR400_2T,
> + [0xa] = DDR333_2T, [0xb] = DDR333_2T},
> + [0xd] = {[0x0] = DDR400_2T, [0x8] = DDR400_2T, [0x1] =
> DDR400_2T,
> + [0x9] = DDR333_2T, [0x4] = DDR400_2T, [0xc] =
> DDR400_2T,
> + [0x5] = DDR333_2T, [0xd] = DDR333_2T},
> + [0x7] = {[0x0] = DDR333_2T, [0x2] = DDR400_2T, [0x1] =
> DDR333_2T,
7,0 above could be DDR333, ie use 1T.
> + [0x3] = DDR400_2T, [0x4] = DDR333_2T, [0x6] =
> DDR400_2T,
> + [0x5] = DDR333_2T, [0x7] = DDR333_2T},
> + [0xf] = {[0x0] = DDR400_2T, [0x1] = DDR400_2T, [0x4] =
> DDR400_2T,
> + [0x5] = DDR333_2T, [0x2] = DDR400_2T, [0x3] =
> DDR400_2T,
> + [0x6] = DDR400_2T, [0x7] = DDR333_2T, [0x8] =
> DDR400_2T,
> + [0x9] = DDR400_2T, [0xc] = DDR400_2T, [0xd] =
> DDR333_2T,
> + [0xa] = DDR333_2T, [0xb] = DDR333_2T, [0xe] =
> DDR333_2T,
> + [0xf] = DDR333_2T},
> + };
The 26094 BKDF PDF refers to "the AMD Athlon™ 64 939 Processor
Motherboard Design Guide, order# 30474" in some of the memory
configuration cases.
It seems that 30474 isn't publically available, maybe someone has
access to it and could check if we should take special considerations
for those cases in coreboot, maybe to choose a lower clock speed to
guarantee reliability?
Acked-by: Peter Stuge <pe...@stuge.se>
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